PMUD

Instance: PMUD
Component: PMUD
Base address: 0x40006000


TOP:PMUD Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL

RW

32

0x0000 0004

0x0000 0000

0x4000 6000

MEASCFG

RW

32

0x0000 0000

0x0000 0004

0x4000 6004

COMPTEST

RW

32

0x0000 0000

0x0000 0008

0x4000 6008

BAT

RO

32

0x0000 0000

0x0000 0028

0x4000 6028

BATUPD

RW

32

0x0000 0000

0x0000 002C

0x4000 602C

TEMP

RO

32

0x0000 0000

0x0000 0030

0x4000 6030

TEMPUPD

RW

32

0x0000 0000

0x0000 0034

0x4000 6034

COMPTESTOUT

RO

32

0x0000 0000

0x0000 0038

0x4000 6038

EVENTMASK

RW

32

0x0000 0000

0x0000 0048

0x4000 6048

EVENT

RW

32

0x0000 0000

0x0000 004C

0x4000 604C

BATTUL

RW

32

0x0000 07FF

0x0000 0050

0x4000 6050

BATTLL

RW

32

0x0000 0000

0x0000 0054

0x4000 6054

TEMPUL

RW

32

0x0000 FFC0

0x0000 0058

0x4000 6058

TEMPLL

RW

32

0x0001 0000

0x0000 005C

0x4000 605C

PREFSYS

RW

32

0x0000 0000

0x0000 0080

0x4000 6080

PREG0

RW

32

0x0000 0000

0x0000 0090

0x4000 6090

PREG1

RW

32

0x0000 0000

0x0000 0094

0x4000 6094

PREG2

RW

32

0x0000 0000

0x0000 0098

0x4000 6098

DCDCCFG

RW

32

0x0000 0000

0x0000 009C

0x4000 609C

DCDCSTAT

RO

32

0x0000 0000

0x0000 00A0

0x4000 60A0

DTBBATMON

RW

32

0x0000 0000

0x0000 00F8

0x4000 60F8

DTBDCDC

RW

32

0x0000 0000

0x0000 00FC

0x4000 60FC

TOP:PMUD Register Descriptions

TOP:PMUD:CTL

Address Offset 0x0000 0000
Physical Address 0x4000 6000 Instance 0x4000 6000
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 HYST_EN Internal. Only to be used through TI provided API. RW 1
1 CALC_EN Internal. Only to be used through TI provided API. RW 0
0 MEAS_EN Internal. Only to be used through TI provided API. RW 0

TOP:PMUD:MEASCFG

Address Offset 0x0000 0004
Physical Address 0x4000 6004 Instance 0x4000 6004
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Internal. Only to be used through TI provided API. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 PER Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 CONT Internal. Only to be used through TI provided API.
0x1 _8CYC Internal. Only to be used through TI provided API.
0x2 _16CYC Internal. Only to be used through TI provided API.
0x3 _32CYC Internal. Only to be used through TI provided API.
RW 0b00

TOP:PMUD:COMPTEST

Address Offset 0x0000 0008
Physical Address 0x4000 6008 Instance 0x4000 6008
Description Enable BATMON comparator test mode.
Note: This register is write-protected based on global lock signal from SYS0 on production devices.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Enable test mode.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:PMUD:BAT

Address Offset 0x0000 0028
Physical Address 0x4000 6028 Instance 0x4000 6028
Description Last Measured Battery Voltage

This register may be read while BATUPD.STAT = 1
Type RO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 INT Integer part:

0x0: 0V + fractional part
...
0x3: 3V + fractional part
0x4: 4V + fractional part		 RO 0b000
7:0 FRAC Fractional part, standard binary fractional encoding.

0x00: .0V
...
0x20: 1/8 = .125V
0x40: 1/4 = .25V
0x80: 1/2 = .5V
...
0xA0: 1/2 + 1/8 = .625V
...
0xFF: Max		 RO 0x00

TOP:PMUD:BATUPD

Address Offset 0x0000 002C
Physical Address 0x4000 602C Instance 0x4000 602C
Description Battery Update

Indicates BAT Updates
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT
0: No update since last clear
1: New battery voltage is present.

Write 1 to clear the status.		 RW 0

TOP:PMUD:TEMP

Address Offset 0x0000 0030
Physical Address 0x4000 6030 Instance 0x4000 6030
Description Temperature

Last Measured Temperature in Degrees Celsius

This register may be read while TEMPUPD.STAT = 1.
Type RO
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16:8 INT Integer part (signed) of temperature value.
Total value = INTEGER + FRACTIONAL
2's complement encoding

0x100: Min value
0x1D8: -40C
0x1FF: -1C
0x00: 0C
0x1B: 27C
0x55: 85C
0xFF: Max value		 RO 0b0 0000 0000
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:PMUD:TEMPUPD

Address Offset 0x0000 0034
Physical Address 0x4000 6034 Instance 0x4000 6034
Description Temperature Update

Indicates TEMP Updates
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT
0: No update since last clear
1: New temperature is present.

Write 1 to clear the status.		 RW 0

TOP:PMUD:COMPTESTOUT

Address Offset 0x0000 0038
Physical Address 0x4000 6038 Instance 0x4000 6038
Description BATMON comparator test mode output.
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STAT Comparator output in test mode.
Value ENUM Name Description
0x0 LOW Low
0x1 HIGH High
RO 0

TOP:PMUD:EVENTMASK

Address Offset 0x0000 0048
Physical Address 0x4000 6048 Instance 0x4000 6048
Description Event Mask
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 TEMP_UPDATE_MASK 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON
0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON		 RW 0
4 BATT_UPDATE_MASK 1: EVENT.BATT_UPDATE contributes to combined event from BATMON
0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON		 RW 0
3 TEMP_BELOW_LL_MASK 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON
0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON		 RW 0
2 TEMP_OVER_UL_MASK 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON
0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON		 RW 0
1 BATT_BELOW_LL_MASK 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON
0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON		 RW 0
0 BATT_OVER_UL_MASK 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON
0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON		 RW 0

TOP:PMUD:EVENT

Address Offset 0x0000 004C
Physical Address 0x4000 604C Instance 0x4000 604C
Description Event
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 TEMP_UPDATE Alias to TEMPUPD.STAT RW 0
4 BATT_UPDATE Alias to BATUPD.STAT RW 0
3 TEMP_BELOW_LL Read:
1: Temperature level is below the lower limit set by TEMPLL.
0: Temperature level is not below the lower limit set by TEMPLL.
Write:
1: Clears the flag
0: No change in the flag		 RW 0
2 TEMP_OVER_UL Read:
1: Temperature level is above the upper limit set by TEMPUL.
0: Temperature level is not above the upper limit set by TEMPUL.
Write:
1: Clears the flag
0: No change in the flag		 RW 0
1 BATT_BELOW_LL Read:
1: Battery level is below the lower limit set by BATTLL.
0: Battery level is not below the lower limit set by BATTLL.
Write:
1: Clears the flag
0: No change in the flag		 RW 0
0 BATT_OVER_UL Read:
1: Battery level is above the upper limit set by BATTUL.
0: Battery level is not above the upper limit set by BATTUL.
Write:
1: Clears the flag
0: No change in the flag		 RW 0

TOP:PMUD:BATTUL

Address Offset 0x0000 0050
Physical Address 0x4000 6050 Instance 0x4000 6050
Description Battery Upper Limit
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 INT Integer part:

0x0: 0V + fractional part
...
0x3: 3V + fractional part
0x4: 4V + fractional part		 RW 0b111
7:0 FRAC Fractional part, standard binary fractional encoding.

0x00: .0V
...
0x20: 1/8 = .125V
0x40: 1/4 = .25V
0x80: 1/2 = .5V
...
0xA0: 1/2 + 1/8 = .625V
...
0xFF: Max		 RW 0xFF

TOP:PMUD:BATTLL

Address Offset 0x0000 0054
Physical Address 0x4000 6054 Instance 0x4000 6054
Description Battery Lower Limit
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 INT Integer part:

0x0: 0V + fractional part
...
0x3: 3V + fractional part
0x4: 4V + fractional part		 RW 0b000
7:0 FRAC Fractional part, standard binary fractional encoding.

0x00: .0V
...
0x20: 1/8 = .125V
0x40: 1/4 = .25V
0x80: 1/2 = .5V
...
0xA0: 1/2 + 1/8 = .625V
...
0xFF: Max		 RW 0x00

TOP:PMUD:TEMPUL

Address Offset 0x0000 0058
Physical Address 0x4000 6058 Instance 0x4000 6058
Description Temperature Upper Limit
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16:8 INT Integer part (signed) of temperature upper limit.
Total value = INTEGER + FRACTIONAL
2's complement encoding

0x100: Min value
0x1D8: -40C
0x1FF: -1C
0x00: 0C
0x1B: 27C
0x55: 85C
0xFF: Max value		 RW 0b0 1111 1111
7:6 FRAC Fractional part of temperature upper limit.
Total value = INTEGER + FRACTIONAL
The encoding is an extension of the 2's complement encoding.

00: 0.0C
01: 0.25C
10: 0.5C
11: 0.75C

For example:
000000001,00 = ( 1+0,00) = 1,00
000000000,11 = ( 0+0,75) = 0,75
000000000,10 = ( 0+0,50) = 0,50
000000000,01 = ( 0+0,25) = 0,25
000000000,00 = ( 0+0,00) = 0,00
111111111,11 = (-1+0,75) = -0,25
111111111,10 = (-1+0,50) = -0,50
111111111,01 = (-1+0,25) = -0,75
111111111,00 = (-1+0,00) = -1,00
111111110,11 = (-2+0,75) = -1,25		 RW 0b11
5:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000

TOP:PMUD:TEMPLL

Address Offset 0x0000 005C
Physical Address 0x4000 605C Instance 0x4000 605C
Description Temperature Lower Limit
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16:8 INT Integer part (signed) of temperature lower limit.
Total value = INTEGER + FRACTIONAL
2's complement encoding

0x100: Min value
0x1D8: -40C
0x1FF: -1C
0x00: 0C
0x1B: 27C
0x55: 85C
0xFF: Max value		 RW 0b1 0000 0000
7:6 FRAC Fractional part of temperature lower limit.
Total value = INTEGER + FRACTIONAL
The encoding is an extension of the 2's complement encoding.

00: 0.0C
01: 0.25C
10: 0.5C
11: 0.75C

For example:
000000001,00 = ( 1+0,00) = 1,00
000000000,11 = ( 0+0,75) = 0,75
000000000,10 = ( 0+0,50) = 0,50
000000000,01 = ( 0+0,25) = 0,25
000000000,00 = ( 0+0,00) = 0,00
111111111,11 = (-1+0,75) = -0,25
111111111,10 = (-1+0,50) = -0,50
111111111,01 = (-1+0,25) = -0,75
111111111,00 = (-1+0,00) = -1,00
111111110,11 = (-2+0,75) = -1,25		 RW 0b00
5:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000

TOP:PMUD:PREFSYS

Address Offset 0x0000 0080
Physical Address 0x4000 6080 Instance 0x4000 6080
Description PMU REFSYS test register. These test bits connect to PMU REFSYS analog module directly.
Note: This register is write-protected except for bits [3:1] based on global lock signal from SYS0 on production devices.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:11 SPARE Spare bits. BATMON comparator enable in test mode is based on COMPTEST.EN bit. RW 0b0 0000
10 TEST10 Connects 1uA IPTAT going to BMON to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
9 TEST9 Connects BMON comparator input to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
8 TEST8 Connects BMON comparator output to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
7 TEST7 Connects 0.8V VREF for pmui2v circuit (IREF) to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
6 TEST6 Connects 0.8V VREF for LRF and HFXT to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
5 TEST5 Connects unbuffered bandgap output to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
4 TEST4 Connects buffered bandgap output to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
3 TEST3 Connects 20uA IREF to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
2 TEST2 Connects 1uA IREF to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
1 TEST1 Connects 4uA IREF to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0
0 TEST0 Connects 2uA IPTAT to va_atb_pmurefsys_a
Value ENUM Name Description
0x0 CLR No connect
0x1 SET Connect
RW 0

TOP:PMUD:PREG0

Address Offset 0x0000 0090
Physical Address 0x4000 6090 Instance 0x4000 6090
Description PMU REG 0 register.
Note: All bits in this register except UDIG_LDO_EN are write-protected based on global lock signal from SYS0 on production devices.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 SOCLDO_ITESTEN SOC LDO current test mode enable bit. Needs to be enabled for DIGLDO and UDIGLDO output current testing.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
9:7 SOCLDO_ATBSEL SOC LDO ATB selection bits.
Value ENUM Name Description
0x0 NC No test muxes connected
0x1 SOCLDO_ITEST Connect selected LDO current output
0x2 SOCLDO_VREF_AMP_OUT Connect reference amplifier output in SOC LDO
0x4 VDD_AON Connect VDD_AON
RW 0b000
6:5 UDIGLDO_ATBSEL UDIGLDO ATB selection bits. This is used to enable test currents out from UDIGLDO through ATEST.
Value ENUM Name Description
0x0 VAL0 No currents out
0x1 VAL1 1/10 of output current
0x2 VAL2 1/5 of output current
0x3 VAL3 3/10 of output current
RW 0b00
4:2 DIGLDO_ATBSEL DIGLDO ATB selection bits. This is used to enable test currents out from DIGLDO through ATEST.
Value ENUM Name Description
0x0 VAL0 No currents out
0x1 VAL1 1/240 of output current
0x2 VAL2 1/120 of output current
0x4 VAL4 1/60 of output current
RW 0b000
1 SPARE Spare bit RW 0
0 UDIGLDO_EN Enable UDIGLDO
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:PMUD:PREG1

Address Offset 0x0000 0094
Physical Address 0x4000 6094 Instance 0x4000 6094
Description PMU REG 1 register.
Note: All bits in this register except DITHER_EN are write-protected based on global lock signal from SYS0 on production devices.
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19 TEST_DCDC_NMOS This bit is used to turn on DCDC NMOS switch. TEST_DCDC_PMOS and TEST_DCDC_NMOS bits should not be set together.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
18 TEST_DCDC_PMOS This bit is used to turn on DCDC PMOS switch. TEST_DCDC_PMOS and TEST_DCDC_NMOS bits should not be set together.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
17 DITHER_EN Enable switching frequency randomizer.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
16 GLDO_AON Keep GLDO always on when enabled. PMUDLC cannot disable GLDO pass gate.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
15 RCHG_BLK_VTRIG_EN Enable/Disable ATEST input to VDDR input of recharge comparator. Used for trimming the recharge voltage reference level.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
14 RCHG_BLK_ATEST_EN Enable/Disable test outputs to recharge comparator block.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
13 RCHG_FORCE_SAMP_VREF Force sample of VREF on sample capacitor.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
12 RCHG_COMP_CLK_DIS Enable/Disable the 32 kHz clock to the recharge comparator.
Value ENUM Name Description
0x0 EN Enable the clock
0x1 DIS Disable the clock
RW 0
11:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
7 SPARE Spare bit. RW 0
6 VDDR_ATBSEL VDDR ATB selection bit. This is used to connect VDDR to ATEST bus.
Set GLDO_ATBSEL = 0x0 first before setting this bit.
Value ENUM Name Description
0x0 DIS Not connected
0x1 EN Connected
RW 0
5 GLDO_EA_BIAS_DIS Disable GLDO error amplifier bias current
Value ENUM Name Description
0x0 ON Bias current remains ON
0x1 OFF Bias current is turned off when GLDO is disabled
RW 0
4:1 GLDO_ATBSEL GLDO ATB selection bits.
Value ENUM Name Description
0x0 NC No GLDO signal connected to test bus
0x1 ERRAMP_OUT GLDO error amp output voltage connected to test bus
0x2 PASSGATE GLDO pass transistor gate voltage connected to test bus
0x4 IB1U GLDO 1uA bias current connected to test bus
0x8 VDDROK VDDR_OK connected to test bus
RW 0x0
0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0

TOP:PMUD:PREG2

Address Offset 0x0000 0098
Physical Address 0x4000 6098 Instance 0x4000 6098
Description PMU REG 2 register.
Note: This register is write-protected based on global lock signal from SYS0 on production devices.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 RSTNMASK This bit is used to mask RSTN pin reset during FLTP1 flash test.
Value ENUM Name Description
0x0 UNMASK Reset is unmasked
0x1 MASK Reset is masked
RW 0
4 DCDC_RCHG_ATBSEL ATB selection between DCDC/GLDO and Recharge block.
Value ENUM Name Description
0x0 DCDC_GLDO Enables DCDC/GLDO test signals selected by GLDO_ATBSEL
0x1 RCHG_BLK Enables input trigger level test signal to the recharge block
RW 0
3:0 PMUREG_ATBSEL PMU REG ATB selection bits.
Value ENUM Name Description
0x0 NC No signal connected to ATEST outputs
0x1 SOCLDOV_A1 SOCLDO voltage on ATEST1
0x2 RESERVED Do not use
0x4 SOCLDOI_A0 SOCLDO current on ATEST0
0x8 DCDC_ATEST0_RCHG_ATEST1 Either DCDC/GLDO or Recharge Block output depending on DCDC_RCHG_ATBSEL bit on ATEST0 and Recharge Block output on ATEST1
RW 0x0

TOP:PMUD:DCDCCFG

Address Offset 0x0000 009C
Physical Address 0x4000 609C Instance 0x4000 609C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Internal. Only to be used through TI provided API. RO 0b0 0000 0000
22:16 LM_HIGHTH Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 MIN Internal. Only to be used through TI provided API.
0x7F MAX Internal. Only to be used through TI provided API.
RW 0b000 0000
15 RESERVED15 Internal. Only to be used through TI provided API. RO 0
14:8 LM_LOWTH Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 MIN Internal. Only to be used through TI provided API.
0x7F MAX Internal. Only to be used through TI provided API.
RW 0b000 0000
7:5 RESERVED5 Internal. Only to be used through TI provided API. RO 0b000
4 ADP_IPEAK_EN Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DISABLE Internal. Only to be used through TI provided API.
0x1 ENABLE Internal. Only to be used through TI provided API.
RW 0
3:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000
0 LMEN Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DISABLE Internal. Only to be used through TI provided API.
0x1 ENABLE Internal. Only to be used through TI provided API.
RW 0

TOP:PMUD:DCDCSTAT

Address Offset 0x0000 00A0
Physical Address 0x4000 60A0 Instance 0x4000 60A0
Description DCDC status register
Type RO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10:8 IPEAK DCDC IPEAK value. This value is same as what is programmed in SYS0.TDCDC.IPEAK when adaptive IPEAK adjustment scheme is not enabled and it shows current IPEAK value applied by hardware when adaptive IPEAK adjustment scheme is enabled.
Value ENUM Name Description
0x0 MIN Minimum value
0x7 MAX Maximum value
RO 0b000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 LOAD This indicates DCDC load meter output value in percentage scale. Valid range is 0x1 to 0x64.
Value ENUM Name Description
0x0 MIN Minimum value
0x7F MAX Maximum value
RO 0b000 0000

TOP:PMUD:DTBBATMON

Address Offset 0x0000 00F8
Physical Address 0x4000 60F8 Instance 0x4000 60F8
Description BATMON DTB MUX selection signal
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 SEL DTB MUX selection signal
Value ENUM Name Description
0x0 DISABLE All DTB outputs driven to zero
0x1 GRP1 GRP1 DTB outputs
0x2 GRP2 GRP2 DTB outputs
0x3 GRP3 GRP3 DTB outputs
0x4 GRP4 GRP4 DTB outputs
0x5 GRP5 GRP5 DTB outputs
0x6 GRP6 GRP6 DTB outputs
0x7 GRP7 GRP7 DTB outputs
0x8 GRP8 GRP8 DTB outputs
0x9 GRP9 GRP9 DTB outputs
0xA GRP10 GRP10 DTB outputs
0xB GRP11 GRP11 DTB outputs
0xC GRP12 GRP12 DTB outputs
0xD GRP13 GRP13 DTB outputs
0xE GRP14 GRP14 DTB outputs
0xF GRP15 GRP15 DTB outputs
RW 0b0 0000

TOP:PMUD:DTBDCDC

Address Offset 0x0000 00FC
Physical Address 0x4000 60FC Instance 0x4000 60FC
Description DCDC DTB MUX selection signal
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SEL DCDC DTB MUX selection signal
Value ENUM Name Description
0x0 DISABLE All DTB outputs driven to zero
0x1 GRP1 GRP1 DTB outputs
0x2 GRP2 GRP2 DTB outputs
0x3 GRP3 GRP3 DTB outputs
0x4 GRP4 GRP 4 DTB outputs
0x5 GRP5 GRP5 DTB outputs
0x6 GRP6 GRP6 DTB outputs
0x7 GRP7 GRP7 DTB outputs
RW 0b000


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