LGPT3

Instance: LGPT3
Component: LGPT3
Base address: 0x40063000


This component is a general purpose timer.
The timer offers
- generation of waveforms and events.
- capture of signal period and duty cycle.
- generation of IR signals.
- decoding of quadrature encoded signals.
- motor control features.

It consists of a
- 16-bit counter.
- 8-bit prescaler
- 3 capture compare channels.
- 3 event outputs.
- 3 capture inputs.

Each channel subscribes to the synchronous event bus. They can control one or more event outputs in both capture and compare modes. PRECFG.TICKSRC selects tick source for the timer.

TOP:LGPT3 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0xDE49 1010

0x0000 0000

0x4006 3000

DESCEX

RO

32

0x0002 18D3

0x0000 0004

0x4006 3004

STARTCFG

RW

32

0x0000 0000

0x0000 0008

0x4006 3008

CTL

RW

32

0x0000 0000

0x0000 000C

0x4006 300C

OUTCTL

RW

32

0x0000 0000

0x0000 0010

0x4006 3010

CNTR

RW

32

0x0000 0000

0x0000 0014

0x4006 3014

PRECFG

RW

32

0x0000 0000

0x0000 0018

0x4006 3018

PREEVENT

RW

32

0x0000 0000

0x0000 001C

0x4006 301C

CHFILT

RW

32

0x0000 0000

0x0000 0020

0x4006 3020

DMA

RW

32

0x0000 0000

0x0000 003C

0x4006 303C

DMARW

RW

32

0x0000 0000

0x0000 0040

0x4006 3040

ADCTRG

RW

32

0x0000 0000

0x0000 0044

0x4006 3044

IOCTL

RW

32

0x0000 0000

0x0000 0048

0x4006 3048

IMASK

RW

32

0x0000 0000

0x0000 0068

0x4006 3068

RIS

RO

32

0x0000 0000

0x0000 006C

0x4006 306C

MIS

RO

32

0x0000 0000

0x0000 0070

0x4006 3070

ISET

WO

32

0x0000 0000

0x0000 0074

0x4006 3074

ICLR

WO

32

0x0000 0000

0x0000 0078

0x4006 3078

IMSET

WO

32

0x0000 0000

0x0000 007C

0x4006 307C

IMCLR

WO

32

0x0000 0000

0x0000 0080

0x4006 3080

EMU

RW

32

0x0000 0000

0x0000 0084

0x4006 3084

C0CFG

RW

32

0x0000 0000

0x0000 00C0

0x4006 30C0

C1CFG

RW

32

0x0000 0000

0x0000 00C4

0x4006 30C4

C2CFG

RW

32

0x0000 0000

0x0000 00C8

0x4006 30C8

PTGT

RW

32

0x0000 0000

0x0000 00FC

0x4006 30FC

PC0CC

RW

32

0x0000 0000

0x0000 0100

0x4006 3100

PC1CC

RW

32

0x0000 0000

0x0000 0104

0x4006 3104

PC2CC

RW

32

0x0000 0000

0x0000 0108

0x4006 3108

TGT

RW

32

0x00FF FFFF

0x0000 013C

0x4006 313C

C0CC

RW

32

0x0000 0000

0x0000 0140

0x4006 3140

C1CC

RW

32

0x0000 0000

0x0000 0144

0x4006 3144

C2CC

RW

32

0x0000 0000

0x0000 0148

0x4006 3148

PTGTNC

RW

32

0x0000 0000

0x0000 017C

0x4006 317C

PC0CCNC

RW

32

0x0000 0000

0x0000 0180

0x4006 3180

PC1CCNC

RW

32

0x0000 0000

0x0000 0184

0x4006 3184

PC2CCNC

RW

32

0x0000 0000

0x0000 0188

0x4006 3188

TGTNC

RW

32

0x00FF FFFF

0x0000 01BC

0x4006 31BC

C0CCNC

RW

32

0x0000 0000

0x0000 01C0

0x4006 31C0

C1CCNC

RW

32

0x0000 0000

0x0000 01C4

0x4006 31C4

C2CCNC

RW

32

0x0000 0000

0x0000 01C8

0x4006 31C8

TOP:LGPT3 Register Descriptions

TOP:LGPT3:DESC

Address Offset 0x0000 0000
Physical Address 0x4006 3000 Instance 0x4006 3000
Description Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier used to uniquely identify this IP. RO 0xDE49
15:12 STDIPOFF Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.

0: Standard IP MMRs do not exist

0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)		 RO 0x1
11:8 INSTIDX IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number. RO 0x0
7:4 MAJREV Major revision of IP. RO 0x1
3:0 MINREV Minor revision of IP. RO 0x0

TOP:LGPT3:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4006 3004 Instance 0x4006 3004
Description Description Extended

This register describes the parameters of the LGPT.
Type RO
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19 HIR Has IR logic. RO 0
18 HDBF Has Dead-Band, Fault, and Park logic. RO 0
17:14 PREW Prescale width. The prescaler can maximum be configured to 2^PREW-1. RO 0x8
13 HQDEC Has Quadrature Decoder. RO 0
12 HCIF Has channel input filter. RO 1
11:8 CIFS Channel input filter size. The prevailing state filter can maximum be configured to 2^CIFS-1. RO 0x8
7 HDMA Has uDMA output and logic. RO 1
6 HINT Has interrupt output and logic. RO 1
5:4 CNTRW Counter bit-width.
The maximum counter value is equal to 2^CNTRW-1.
Value ENUM Name Description
0x0 CNTR16 16-bit counter.
0x1 CNTR24 24-bit counter.
0x2 CNTR32 32-bit counter.
0x3 RESERVED RESERVED
RO 0b01
3:0 NCH Number of channels. RO 0x3

TOP:LGPT3:STARTCFG

Address Offset 0x0000 0008
Physical Address 0x4006 3008 Instance 0x4006 3008
Description Start Configuration

This register is only for when CTL.MODE is configured to one of the SYNC modes.
This register defines when this LGPT starts.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 LGPT0 LGPT start
Value ENUM Name Description
0x0 EV_SYNC LGPT starts when synchronized event input is high. Configured here [EVTSVT:LGPTSYNCSEL].
RW 0b00

TOP:LGPT3:CTL

Address Offset 0x0000 000C
Physical Address 0x4006 300C Instance 0x4006 300C
Description Timer Control
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2RST Channel 2 reset.
Value ENUM Name Description
0x0 NOEFF No effect.
0x1 RST Reset C2CC, PC2CC, and C2CFG.
WO 0
9 C1RST Channel 1 reset.
Value ENUM Name Description
0x0 NOEFF No effect.
0x1 RST Reset C1CC, PC1CC, and C1CFG.
WO 0
8 C0RST Channel 0 reset.
Value ENUM Name Description
0x0 NOEFF No effect.
0x1 RST Reset C0CC, PC0CC, and C0CFG.
WO 0
7:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
5 INTP Interrupt Phase.
This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set.
Value ENUM Name Description
0x0 EARLY RIS.TGT and RIS.ZERO are set one system clock cycle after CNTR = TARGET/ZERO.
0x1 LATE RIS.TGT and RIS.ZERO are set one timer clock cycle after CNTR = TARGET/ZERO.
RW 0
4:3 CMPDIR Compare direction.

This bit field controls the direction the counter must have in order to set the [RIS.CnCC] channel interrupts. This bitfield is only relevant if [CnCFG.CCACT] is configured to a compare action.
Value ENUM Name Description
0x0 BOTH Compare RIS fields are set on up count and down count.
0x1 UP Compare RIS fields are only set on up count.
0x2 DOWN Compare RIS fields are only set on down count.
0x3 RESERVED RESERVED
RW 0b00
2:0 MODE Timer mode control

The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER.

When writing MODE all internally queued updates to the channels and TGT is cleared.

When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example C0CFG.
Value ENUM Name Description
0x0 DIS Disable timer. Updates to counter, channels, and events stop.
0x1 UP_ONCE Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS.
0x2 UP_PER Count up periodically. The timer increments from 0 to target value, repeatedly.

Period = (target value + 1) * timer clock period
0x3 UPDWN_PER Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly.

Period = (target value * 2) * timer clock period
0x4 QDEC The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectivly as PHA, PHB and IDX inputs. IDX can be turned off by setting C2CFG.EDGE = NONE.
The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in PRECFG.
0x5 SYNC_UP_ONCE Start counting up once synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_ONCE automatically.
It then functions as a normal timer in CTL.MODE = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS.
0x6 SYNC_UP_PER Start counting up periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_PER automatically.
It then operates as a normal timer in CTL.MODE = UP_PER, incrementing from 0 to target value, repeatedly.

Period = (target value * 2) * timer clock period
0x7 SYNC_UPDWN_PER Start counting up and down periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UPDWN_PER automatically.
It then operates as a normal timer in CTL.MODE = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly.

Period = (target value * 2) * timer clock period
RW 0b000

TOP:LGPT3:OUTCTL

Address Offset 0x0000 0010
Physical Address 0x4006 3010 Instance 0x4006 3010
Description Output Control

Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected.

An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time.

All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an aditional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see IOCTL.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 SETOUT2 Set output 2.

Write 1 to set output 2.		 WO 0
4 CLROUT2 Clear output 2.

Write 1 to clear output 2.		 WO 0
3 SETOUT1 Set output 1.

Write 1 to set output 1.		 WO 0
2 CLROUT1 Clear output 1.

Write 1 to clear output 1.		 WO 0
1 SETOUT0 Set output 0.

Write 1 to set output 0.		 WO 0
0 CLROUT0 Clear output 0.

Write 1 to clear output 0.		 WO 0

TOP:LGPT3:CNTR

Address Offset 0x0000 0014
Physical Address 0x4006 3014 Instance 0x4006 3014
Description Counter
The counter of this timer. After CTL.MODE is set the counter updates at the rate specified in PRECFG.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Current counter value.
If CTL.MODE = QDEC this can be used to set the initial counter value during QDEC.		 RW 0x00 0000

TOP:LGPT3:PRECFG

Address Offset 0x0000 0018
Physical Address 0x4006 3018 Instance 0x4006 3018
Description Clock Prescaler Configuration

This register is used to set the timer clock period. The prescaler is a counter which counts down from the value TICKDIV. When the prescaler counter reaches zero, CNTR is updated. The field TICKDIV effectively divides the prescaler tick source. The timer clock frequency can be calculated as TICKSRC/(TICKDIV+1).
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 TICKDIV Tick division.

TICKDIV determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by TICKSRC divided by (TICKDIV + 1). This inverse is the timer clock period.

0x00: Divide by 1.
0x01: Divide by 2.
...
0xFF: Divide by 256.		 RW 0x00
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1:0 TICKSRC Prescaler tick source.

TICKSRC determines the source which decrements the prescaler.
Value ENUM Name Description
0x0 CLK Prescaler is updated at the system clock.
0x1 RISE_TICK Prescaler is updated at the rising edge of TICKEN.
0x2 FALL_TICK Prescaler is updated at the falling edge of TICKEN.
0x3 BOTH_TICK Prescaler is updated at both edges of TICKEN.
RW 0b00

TOP:LGPT3:PREEVENT

Address Offset 0x0000 001C
Physical Address 0x4006 301C Instance 0x4006 301C
Description Prescaler Event

This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 VAL Sets the HIGH time of the prescaler event output.

Event goes high when the prescaler counter equals VAL. Event goes low when prescaler counter is 0.

Note:
- Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC.
- If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer.		 RW 0x00

TOP:LGPT3:CHFILT

Address Offset 0x0000 0020
Physical Address 0x4006 3020 Instance 0x4006 3020
Description Channel Input Filter

This register is used to configure the filter on the channel inputs. The configuration is for all inputs.
The filter is enabled when a channel is in capture mode.

The input to the filter is passed to the edge detection logic if LOAD + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample.
If two consecutive samples are unequal, the filter counter restarts from LOAD.
If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic.

The channel filter should only be configured while the CTL.MODE = DIS. Configuring the filter while the timer is running can result in unexpected behavior.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:8 LOAD The input of the channel filter is passed to the edge detection logic after LOAD + 1 consecutive equal samples. RW 0x00
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1:0 MODE Channel filter mode
Value ENUM Name Description
0x0 BYPASS Filter is bypassed. No Filter is used.
0x1 CLK Filter is clocked by system clock.
0x2 TICKSRC Filter is clocked by PRECFG.TICKSRC.
0x3 TIMERCLK Filter is clocked by timer clock.
RW 0b00

TOP:LGPT3:DMA

Address Offset 0x0000 003C
Physical Address 0x4006 303C Instance 0x4006 303C
Description Direct Memory Accsess

This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write).
Choose DMA request source by setting the REQ field. The setting of the corresponding interrupt in the RIS registers also sets the DMA request.
Upon a DMA request defined by REQ an internal address pointer is set to RWADDR*4. Every access to DMARW will increment the internal pointer by 4 such that the next DMA access will be to the next register.
The internal pointer will stop after RWCNTR increments. Further access will be ignored.
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:16 RWCNTR The read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the DMARW register. For each DMA access to DMARW an internal counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR is the final register address which can be accessed by the DMA. RW 0x0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:8 RWADDR The base address which the DMA access when reading/writing DMARW. The base address is set by taking the 9 LSB of the physical address and divide by 4.
For example, if you wanted the RWADDR to point to the PTGT register you should set RWADDR = 0x0FC/4.		 RW 0b000 0000
7:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
3:0 REQ
Value ENUM Name Description
0x0 DIS Disabled
0x1 TGT Setting of RIS.TGT generates a DMA request.
0x2 ZERO Setting of RIS.ZERO generates a DMA request.
0x3 FAULT Setting of RIS.FAULT generates a DMA request.
0x4 C0CC Setting of RIS.C0CC generates a DMA request.
0x5 C1CC Setting of RIS.C1CC generates a DMA request.
0x6 C2CC Setting of RIS.C2CC generates a DMA request.
0x7 C3CC Setting of RIS.C3CC generates a DMA request.
0x8 C4CC Setting of RIS.C4CC generates a DMA request.
0x9 C5CC Setting of RIS.C5CC generates a DMA request.
0xA C6CC Setting of RIS.C6CC generates a DMA request.
0xB C7CC Setting of RIS.C7CC generates a DMA request.
0xC C8CC Setting of RIS.C8CC generates a DMA request.
0xD C9CC Setting of RIS.C9CC generates a DMA request.
0xE C10CC Setting of RIS.C10CC generates a DMA request.
0xF C11CC Setting of RIS.C11CC generates a DMA request.
RW 0x0

TOP:LGPT3:DMARW

Address Offset 0x0000 0040
Physical Address 0x4006 3040 Instance 0x4006 3040
Description Direct Memory Access

This register is used by the DMA to access (read/write) register inside this LGPT module.
Each access to this register will increment the internal DMA address counter. See DMA for description.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL DMA read write value.

The value that is read/written from/to the registers.		 RW 0x00 0000

TOP:LGPT3:ADCTRG

Address Offset 0x0000 0044
Physical Address 0x4006 3044 Instance 0x4006 3044
Description ADC Trigger

This register is used to enable ADC trigger from the timer.
Choose ADC trigger source by setting the SRC field. The setting of the corresponding interrupt in the RIS registers also sets the ADC trigger.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SRC
Value ENUM Name Description
0x0 DIS Disabled
0x1 TGT Setting of RIS.TGT generates an ADC trigger.
0x2 ZERO Setting of RIS.ZERO generates an ADC trigger.
0x3 FAULT Setting of RIS.FAULT generates an ADC trigger.
0x4 C0CC Setting of RIS.C0CC generates an ADC trigger.
0x5 C1CC Setting of RIS.C1CC generates an ADC trigger.
0x6 C2CC Setting of RIS.C2CC generates an ADC trigger.
0x7 C3CC Setting of RIS.C3CC generates an ADC trigger.
0x8 C4CC Setting of RIS.C4CC generates an ADC trigger.
0x9 C5CC Setting of RIS.C5CC generates an ADC trigger.
0xA C6CC Setting of RIS.C6CC generates an ADC trigger.
0xB C7CC Setting of RIS.C7CC generates an ADC trigger.
0xC C8CC Setting of RIS.C8CC generates an ADC trigger.
0xD C9CC Setting of RIS.C9CC generates an ADC trigger.
0xE C10CC Setting of RIS.C10CC generates an ADC trigger.
0xF C11CC Setting of RIS.C11CC generates an ADC trigger.
RW 0x0

TOP:LGPT3:IOCTL

Address Offset 0x0000 0048
Physical Address 0x4006 3048 Instance 0x4006 3048
Description IO Controller

This register overrides the IO outputs.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11:10 COUT2 IO complementary output 2 control

This bit field controls IO complementary output 2.
Value ENUM Name Description
0x0 NRM Normal output. The IO complementary output is not changed.
0x1 LOW Driven low. The IO complementary output is driven low.
0x2 HIGH Driven high. The IO complementary output is driven high.
0x3 INV Inverted value. The IO complementary output is inverted.
RW 0b00
9:8 OUT2 IO output 2 control

This bit field controls IO output 2.
Value ENUM Name Description
0x0 NRM Normal output. The IO output is not changed.
0x1 LOW Driven low. The IO output is driven low.
0x2 HIGH Driven high. The IO output is driven high.
0x3 INV Inverted value. The IO output is inverted.
RW 0b00
7:6 COUT1 IO complementary output 1 control

This bit field controls IO complementary output 1.
Value ENUM Name Description
0x0 NRM Normal output. The IO complementary output is not changed.
0x1 LOW Driven low. The IO complementary output is driven low.
0x2 HIGH Driven high. The IO complementary output is driven high.
0x3 INV Inverted value. The IO complementary output is inverted.
RW 0b00
5:4 OUT1 IO output 1 control

This bit field controls IO output 1.
Value ENUM Name Description
0x0 NRM Normal output. The IO output is not changed.
0x1 LOW Driven low. The IO output is driven low.
0x2 HIGH Driven high. The IO output is driven high.
0x3 INV Inverted value. The IO output is inverted.
RW 0b00
3:2 COUT0 IO complementary output 0 control

This bit field controls IO complementary output 0.
Value ENUM Name Description
0x0 NRM Normal output. The IO complementary output is not changed.
0x1 LOW Driven low. The IO complementary output is driven low.
0x2 HIGH Driven high. The IO complementary output is driven high.
0x3 INV Inverted value. The IO complementary output is inverted.
RW 0b00
1:0 OUT0 IO output 0 control

This bit field controls IO output 0.
Value ENUM Name Description
0x0 NRM Normal output. The IO output is not changed.
0x1 LOW Driven low. The IO output is driven low.
0x2 HIGH Driven high. The IO output is driven high.
0x3 INV Inverted value. The IO output is inverted.
RW 0b00

TOP:LGPT3:IMASK

Address Offset 0x0000 0068
Physical Address 0x4006 3068 Instance 0x4006 3068
Description Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Enable RIS.C2CC interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
9 C1CC Enable RIS.C1CC interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
8 C0CC Enable RIS.C0CC interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Enable RIS.FAULT interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
5 IDX Enable RIS.IDX interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
4 DIRCHNG Enable RIS.DIRCHNG interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
3 CNTRCHNG Enable RIS.CNTRCHNG interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
2 DBLTRANS Enable RIS.DBLTRANS interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
1 ZERO Enable RIS.ZERO interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
0 TGT Enable RIS.TGT interrupt.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:LGPT3:RIS

Address Offset 0x0000 006C
Physical Address 0x4006 306C Instance 0x4006 306C
Description Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type RO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Status of the C2CC interrupt. The interrupt is set when C2CC has capture or compare event.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
9 C1CC Status of the C1CC interrupt. The interrupt is set when C1CC has capture or compare event.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
8 C0CC Status of the C0CC interrupt. The interrupt is set when C0CC has capture or compare event.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Status of the FAULT interrupt. The interrupt is set immediately on active fault input.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
5 IDX Status of the IDX interrupt. The interrupt is set when IDX is active.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
4 DIRCHNG Status of the DIRCHNG interrupt. The interrupt is set when the direction of the counter changes.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
3 CNTRCHNG Status of the CNTRCHNG interrupt. The interrupt is set when the counter increments or decrements.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
2 DBLTRANS Status of the DBLTRANS interrupt. The interrupt is set when a double transition has happened during QDEC mode.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
1 ZERO Status of the ZERO interrupt. The interrupt is set when CNTR = 0.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
0 TGT Status of the TGT interrupt. The interrupt is set when CNTR = TGT.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0

TOP:LGPT3:MIS

Address Offset 0x0000 0070
Physical Address 0x4006 3070 Instance 0x4006 3070
Description Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type RO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Masked status of the RIS.C2CC interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
9 C1CC Masked status of the RIS.C1CC interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
8 C0CC Masked status of the RIS.C0CC interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Masked status of the RIS.FAULT interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
5 IDX Masked status of the RIS.IDX interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
4 DIRCHNG Masked status of the RIS.DIRCHNG interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
3 CNTRCHNG Masked status of the RIS.CNTRCHNG interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
2 DBLTRANS Masked status of the RIS.DBLTRANS interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
1 ZERO Masked status of the RIS.ZERO interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0
0 TGT Masked status of the RIS.TGT interrupt.
Value ENUM Name Description
0x0 CLR Cleared
0x1 SET Set
RO 0

TOP:LGPT3:ISET

Address Offset 0x0000 0074
Physical Address 0x4006 3074 Instance 0x4006 3074
Description Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Type WO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Set the RIS.C2CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
9 C1CC Set the RIS.C1CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
8 C0CC Set the RIS.C0CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Set the RIS.FAULT interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
5 IDX Set the RIS.IDX interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
4 DIRCHNG Set the RIS.DIRCHNG interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
3 CNTRCHNG Set the RIS.CNTRCHNG interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
2 DBLTRANS Set the RIS.DBLTRANS interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
1 ZERO Set the RIS.ZERO interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
0 TGT Set the RIS.TGT interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0

TOP:LGPT3:ICLR

Address Offset 0x0000 0078
Physical Address 0x4006 3078 Instance 0x4006 3078
Description Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Type WO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Clear the RIS.C2CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
9 C1CC Clear the RIS.C1CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
8 C0CC Clear the RIS.C0CC interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Clear the RIS.FAULT interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
5 IDX Clear the RIS.IDX interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
4 DIRCHNG Clear the RIS.DIRCHNG interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
3 CNTRCHNG Clear the RIS.CNTRCHNG interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
2 DBLTRANS Clear the RIS.DBLTRANS interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
1 ZERO Clear the RIS.ZERO interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
0 TGT Clear the RIS.TGT interrupt.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0

TOP:LGPT3:IMSET

Address Offset 0x0000 007C
Physical Address 0x4006 307C Instance 0x4006 307C
Description Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.
Type WO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Set the MIS.C2CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
9 C1CC Set the MIS.C1CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
8 C0CC Set the MIS.C0CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Set the MIS.FAULT mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
5 IDX Set the MIS.IDX mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
4 DIRCHNG Set the MIS.DIRCHNG mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
3 CNTRCHNG Set the MIS.CNTRCHNG mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
2 DBLTRANS Set the MIS.DBLTRANS mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
1 ZERO Set the MIS.ZERO mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0
0 TGT Set the MIS.TGT mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 SET Set
WO 0

TOP:LGPT3:IMCLR

Address Offset 0x0000 0080
Physical Address 0x4006 3080 Instance 0x4006 3080
Description Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.
Type WO
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 C2CC Clear the MIS.C2CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
9 C1CC Clear the MIS.C1CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
8 C0CC Clear the MIS.C0CC mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 FAULT Clear the MIS.FAULT mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
5 IDX Clear the MIS.IDX mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
4 DIRCHNG Clear the MIS.DIRCHNG mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
3 CNTRCHNG Clear the MIS.CNTRCHNG mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
2 DBLTRANS Clear the MIS.DBLTRANS mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
1 ZERO Clear the MIS.ZERO mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0
0 TGT Clear the MIS.TGT mask.
Value ENUM Name Description
0x0 NO_EFFECT No effect
0x1 CLR Clear
WO 0

TOP:LGPT3:EMU

Address Offset 0x0000 0084
Physical Address 0x4006 3084 Instance 0x4006 3084
Description Debug control

This register can be used to freeze the timer when CPU halts when HALT is set to 1. When HALT is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, PARK, if the timer has this register, should be configured additionally. If this timer does not have the PARK register a predefined output value during CPU halt is not possible.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 CTL Halt control.

Configure when the counter shall stop upon CPU halt. This bitfield only applies if HALT = 1.
Value ENUM Name Description
0x0 IMMEDIATE Immediate reaction. The counter stops immediately on debug halt.
0x1 ZERCOND Zero condition. The counter stops when CNTR = 0.
RW 0
0 HALT Halt LGPT when CPU is halted in debug.
Value ENUM Name Description
0x0 DIS Disable.
0x1 EN Enable.
RW 0

TOP:LGPT3:C0CFG

Address Offset 0x0000 00C0
Physical Address 0x4006 30C0 Instance 0x4006 30C0
Description Channel 0 Configuration

This register configures channel function and enables outputs.

Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.

The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.

Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 OUT2 Output 2 enable.

When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 0 does not control output 2.
0x1 EN Channel 0 controls output 2.
RW 0
9 OUT1 Output 1 enable.

When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 0 does not control output 1.
0x1 EN Channel 0 controls output 1.
RW 0
8 OUT0 Output 0 enable.

When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 0 does not control output 0.
0x1 EN Channel 0 controls output 0.
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 INPUT Select channel input.
Value ENUM Name Description
0x0 EV Event fabric
0x1 IO IO controller
RW 0
5:4 EDGE Determines the edge that triggers the channel input event. This happens post filter.
Value ENUM Name Description
0x0 NONE Input is turned off.
0x1 RISE Input event is triggered at rising edge.
0x2 FALL Input event is triggered at falling edge.
0x3 BOTH Input event is triggered at both edges.
RW 0b00
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C0CC.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL.
- Disable channel.

Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled outputs when C0CC.VAL = CNTR.VAL.
- Disable channel.

The output is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.

Set enabled outputs and RIS.C0CC when C0CC.VAL contains signal period and PC0CC.VAL contains signal pulse width.

Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C0CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When C0CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C0CC.VAL / TGT.VAL ).

When C0CC.VAL > TGT.VAL:
Duty cycle = 0.

Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When C0CC.VAL <= TGT.VAL:
Duty cycle = C0CC.VAL / ( TGT.VAL + 1 ).

When C0CC.VAL > TGT.VAL:
Duty cycle = 1.

Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when C0CC.VAL = CNTR.VAL.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled outputs when C0CC.VAL = CNTR.VAL.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled outputs when C0CC.VAL = CNTR.VAL.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled outputs when C0CC.VAL = CNTR.VAL.

The output is high for two timer clock periods.
RW 0x0

TOP:LGPT3:C1CFG

Address Offset 0x0000 00C4
Physical Address 0x4006 30C4 Instance 0x4006 30C4
Description Channel 1 Configuration

This register configures channel function and enables outputs.

Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.

The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.

Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 OUT2 Output 2 enable.

When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 1 does not control output 2.
0x1 EN Channel 1 controls output 2.
RW 0
9 OUT1 Output 1 enable.

When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 1 does not control output 1.
0x1 EN Channel 1 controls output 1.
RW 0
8 OUT0 Output 0 enable.
When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 1 does not control output 0.
0x1 EN Channel 1 controls output 0.
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 INPUT Select channel input.
Value ENUM Name Description
0x0 EV Event fabric
0x1 IO IO controller
RW 0
5:4 EDGE Determines the edge that triggers the channel input event. This happens post filter.
Value ENUM Name Description
0x0 NONE Input is turned off.
0x1 RISE Input event is triggered at rising edge.
0x2 FALL Input event is triggered at falling edge.
0x3 BOTH Input event is triggered at both edges.
RW 0b00
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C1CC.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL.
- Disable channel.

Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled outputs when C1CC.VAL = CNTR.VAL.
- Disable channel.

The output is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.

Set enabled outputs and RIS.C1CC when C1CC.VAL contains signal period and PC1CC.VAL contains signal pulse width.

Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C1CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When C1CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C1CC.VAL / TGT.VAL ).

When C1CC.VAL > TGT.VAL:
Duty cycle = 0.

Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When C1CC.VAL <= TGT.VAL:
Duty cycle = C1CC.VAL / ( TGT.VAL + 1 ).

When C1CC.VAL > TGT.VAL:
Duty cycle = 1.

Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when C1CC.VAL = CNTR.VAL.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled outputs when C1CC.VAL = CNTR.VAL.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled outputs when C1CC.VAL = CNTR.VAL.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled outputs when C1CC.VAL = CNTR.VAL.

The output is high for two timer clock periods.
RW 0x0

TOP:LGPT3:C2CFG

Address Offset 0x0000 00C8
Physical Address 0x4006 30C8 Instance 0x4006 30C8
Description Channel 2 Configuration

This register configures channel function and enables outputs.

Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.

The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.

The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.

Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 OUT2 Output 2 enable.

When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 2 does not control output 2.
0x1 EN Channel 2 controls output 2.
RW 0
9 OUT1 Output 1 enable.

When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 2 does not control output 1.
0x1 EN Channel 2 controls output 1.
RW 0
8 OUT0 Output 0 enable.

When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event.
Value ENUM Name Description
0x0 DIS Channel 2 does not control output 0.
0x1 EN Channel 2 controls output 0.
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 INPUT Select channel input.
Value ENUM Name Description
0x0 EV Event fabric
0x1 IO IO controller
RW 0
5:4 EDGE Determines the edge that triggers the channel input event. This happens post filter.
Value ENUM Name Description
0x0 NONE Input is turned off.
0x1 RISE Input event is triggered at rising edge.
0x2 FALL Input event is triggered at falling edge.
0x3 BOTH Input event is triggered at both edges.
RW 0b00
3:0 CCACT Capture-Compare action.

Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C2CC.
Value ENUM Name Description
0x0 DIS Disable channel.
0x1 SET_ON_CAPT_DIS Set on capture, and then disable channel.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL.
- Disable channel.

Primary use scenario is to select this function before starting the timer.
Follow these steps to select this function while CTL.MODE is different from DIS:
- Set CCACT to SET_ON_CAPT with no output enable.
- Configure INPUT (optional).
- Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.
0x2 CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0.
0x3 SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.

Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0.
0x4 CLR_ON_CMP_DIS Clear on compare, and then disable channel.

Channel function sequence:
- Clear enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
0x5 SET_ON_CMP_DIS Set on compare, and then disable channel.

Channel function sequence:
- Set enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
0x6 TGL_ON_CMP_DIS Toggle on compare, and then disable channel.

Channel function sequence:
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.
0x7 PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.

Channel function sequence:
- Pulse enabled outputs when C2CC.VAL = CNTR.VAL.
- Disable channel.

The output is high for two timer clock periods.
0x8 PER_PULSE_WIDTH_MEAS Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE.

Set enabled outputs and RIS.C2CC when C2CC.VAL contains signal period and PC2CC.VAL contains signal pulse width.

Notes:
- Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
- The counter restarts in the selected timer mode when C2CC.VAL contains the signal period.
- If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
- To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT.

Signal property requirements:
- Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period.
- Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period.
- Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period.
0x9 SET_ON_CAPT Set on capture repeatedly.

Channel function sequence:
- Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL.
0xA CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When C2CC.VAL <= TGT.VAL:
Duty cycle = 1 - ( C2CC.VAL / TGT.VAL ).

When C2CC.VAL > TGT.VAL:
Duty cycle = 0.

Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0.
0xB SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.

Channel function sequence:
- Set enabled outputs when CNTR.VAL = 0.
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When C2CC.VAL <= TGT.VAL:
Duty cycle = C2CC.VAL / ( TGT.VAL + 1 ).

When C2CC.VAL > TGT.VAL:
Duty cycle = 1.

Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0.
0xC CLR_ON_CMP Clear on compare repeatedly.

Channel function sequence:
- Clear enabled outputs when C2CC.VAL = CNTR.VAL.
0xD SET_ON_CMP Set on compare repeatedly.

Channel function sequence:
- Set enabled outputs when C2CC.VAL = CNTR.VAL.
0xE TGL_ON_CMP Toggle on compare repeatedly.

Channel function sequence:
- Toggle enabled outputs when C2CC.VAL = CNTR.VAL.
0xF PULSE_ON_CMP Pulse on compare repeatedly.

Channel function sequence:
- Pulse enabled outputs when C2CC.VAL = CNTR.VAL.

The output is high for two timer clock periods.
RW 0x0

TOP:LGPT3:PTGT

Address Offset 0x0000 00FC
Physical Address 0x4006 30FC Instance 0x4006 30FC
Description Pipeline Target
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.


If CTL.MODE != QDEC.
Target value for next counter period.
The timer will copy PTGT.VAL to TGT.VAL on the upcoming CNTR zero crossing only if PTGT.VAL has been written. The copy does not happen when restarting the timer.
This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.

If CTL.MODE = QDEC
The CNTR value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, CNTR is loaded with zero on IDX.
In this mode the VALUE is not loaded into TGT on zero crossing.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL The pipleline target value. RW 0x00 0000

TOP:LGPT3:PC0CC

Address Offset 0x0000 0100
Physical Address 0x4006 3100 Instance 0x4006 3100
Description Pipeline Channel 0 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C0CC interrupt.

Compare mode:
An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:PC1CC

Address Offset 0x0000 0104
Physical Address 0x4006 3104 Instance 0x4006 3104
Description Pipeline Channel 1 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C1CC interrupt.

Compare mode:
An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:PC2CC

Address Offset 0x0000 0108
Physical Address 0x4006 3108 Instance 0x4006 3108
Description Pipeline Channel 2 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C2CC interrupt.

Compare mode:
An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:TGT

Address Offset 0x0000 013C
Physical Address 0x4006 313C Instance 0x4006 313C
Description Target

User defined counter target.
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL User defined counter target value. RW 0xFF FFFF

TOP:LGPT3:C0CC

Address Offset 0x0000 0140
Physical Address 0x4006 3140 Instance 0x4006 3140
Description Channel 0 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C0CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000

TOP:LGPT3:C1CC

Address Offset 0x0000 0144
Physical Address 0x4006 3144 Instance 0x4006 3144
Description Channel 1 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C1CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000

TOP:LGPT3:C2CC

Address Offset 0x0000 0148
Physical Address 0x4006 3148 Instance 0x4006 3148
Description Channel 2 Capture Compare
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will clear the RIS.C2CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000

TOP:LGPT3:PTGTNC

Address Offset 0x0000 017C
Physical Address 0x4006 317C Instance 0x4006 317C
Description Pipeline Target No Clear

Use this register to read or write to PTGT without clearing the RIS.ZERO and RIS.TGT interrupt.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL A read or write to this register will not clear the RIS.TGT interrupt.

If CTL.MODE != QDEC.
Target value for next counter period.
The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not happen when restarting the timer.
This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.

If CTL.MODE = QDEC.
The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when CNTR.VAL becomes 0.		 RW 0x00 0000

TOP:LGPT3:PC0CCNC

Address Offset 0x0000 0180
Physical Address 0x4006 3180 Instance 0x4006 3180
Description Pipeline Channel 0 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C0CC interrupt.

Compare mode:
An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:PC1CCNC

Address Offset 0x0000 0184
Physical Address 0x4006 3184 Instance 0x4006 3184
Description Pipeline Channel 1 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C1CC interrupt.

Compare mode:
An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:PC2CCNC

Address Offset 0x0000 0188
Physical Address 0x4006 3188 Instance 0x4006 3188
Description Pipeline Channel 2 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Pipeline Capture Compare value.

User defined pipeline compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C2CC interrupt.

Compare mode:
An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.

Capture mode:
When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE.		 RW 0x00 0000

TOP:LGPT3:TGTNC

Address Offset 0x0000 01BC
Physical Address 0x4006 31BC Instance 0x4006 31BC
Description Target No Clear

Use this register to read or write to TGT without clearing the RIS.ZERO and RIS.TGT interrupt.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL User defined counter target value. RW 0xFF FFFF

TOP:LGPT3:C0CCNC

Address Offset 0x0000 01C0
Physical Address 0x4006 31C0 Instance 0x4006 31C0
Description Channel 0 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C0CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000

TOP:LGPT3:C1CCNC

Address Offset 0x0000 01C4
Physical Address 0x4006 31C4 Instance 0x4006 31C4
Description Channel 1 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C1CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000

TOP:LGPT3:C2CCNC

Address Offset 0x0000 01C8
Physical Address 0x4006 31C8 Instance 0x4006 31C8
Description Channel 2 Capture Compare No Clear
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 VAL Capture Compare value.

User defined compare value or channel-updated capture value.

A read or write to this register will not clear the RIS.C2CC interrupt.

Compare mode:
VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal.

Capture mode:
The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value.		 RW 0x00 0000


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