I2C0

Instance: I2C0
Component: I2C
Base address: 0x40038000


I2C IP

TOP:I2C0 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

TOAR

RW

32

0x0000 0000

0x0000 0000

0x4003 8000

TSTAT_CTL

RW

32

0x0000 0000

0x0000 0004

0x4003 8004

TDR

RW

32

0x0000 0000

0x0000 0008

0x4003 8008

TIMR

RW

32

0x0000 0000

0x0000 000C

0x4003 800C

TRIS

RO

32

0x0000 0000

0x0000 0010

0x4003 8010

TMIS

RO

32

0x0000 0000

0x0000 0014

0x4003 8014

TICR

RW

32

0x0000 0000

0x0000 0018

0x4003 8018

CSA

RW

32

0x0000 0000

0x0000 0800

0x4003 8800

CSTAT_CTL

RW

32

0x0000 0020

0x0000 0804

0x4003 8804

CDR

RW

32

0x0000 0000

0x0000 0808

0x4003 8808

CTPR

RW

32

0x0000 0001

0x0000 080C

0x4003 880C

CIMR

RW

32

0x0000 0000

0x0000 0810

0x4003 8810

CRIS

RO

32

0x0000 0000

0x0000 0814

0x4003 8814

CMIS

RO

32

0x0000 0000

0x0000 0818

0x4003 8818

CICR

RW

32

0x0000 0000

0x0000 081C

0x4003 881C

CCR

RW

32

0x0000 0000

0x0000 0820

0x4003 8820

TOP:I2C0 Register Descriptions

TOP:I2C0:TOAR

Address Offset 0x0000 0000
Physical Address 0x4003 8000 Instance 0x4003 8000
Description Target Own Address
This register consists of seven address bits that identify this I2C device on the I2C bus.
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6:0 OAR I2C target own address. This field specifies bits a6 through a0 of the target address. RW 0b000 0000

TOP:I2C0:TSTAT_CTL

Address Offset 0x0000 0004
Physical Address 0x4003 8004 Instance 0x4003 8004
Description Target Control and Target Status
This register functions as a control register when written, and a status register when read.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 FBR First byte received.
This bit is only applicable when the RREQ bit is set and is automatically cleared when data has been read from the SDR register.
Note: This bit is not used for target transmit operations.
Value ENUM Name Description
0x0 CLEAR The first byte following the target's own address has not been received.
0x1 SET The first byte following the target's own address has been received.
RO 0
1 TREQ Transmit request
Value ENUM Name Description
0x0 CLEAR No outstanding transmit request
0x1 SET The I2C controller has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the SDR register
RO 0
0 RREQ_DA This field reflects the Receive Request status when read and sets the Device Active control when written.
When read:
0 - No outstanding receive data
1 - The I2C controller has outstanding receive data from the I2C controller and is using clock stretching to delay the controller until data has been read from the SDR register

When written:
0 - Disables the I2C target operation
1 - Enables the I2C target operation		 RW 0

TOP:I2C0:TDR

Address Offset 0x0000 0008
Physical Address 0x4003 8008 Instance 0x4003 8008
Description Target Data
This register contains the data to be transmitted when in the Target Transmit state, and the data received
when in the Target Receive state.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA Data for transfer. This field contains the data for transfer during a target receive or a transmit operation. When written, the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write to the controller for transmit or by an external controller to the target for receive. RW 0x00

TOP:I2C0:TIMR

Address Offset 0x0000 000C
Physical Address 0x4003 800C Instance 0x4003 800C
Description Target Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 STOPIM Stop condition interrupt mask
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
1 STARTIM Start condition interrupt mask
Value ENUM Name Description
0x0 DIS Disable Interrupt Mask
0x1 EN Enable Interrupt Mask
RW 0
0 DATAIM Data interrupt mask
Value ENUM Name Description
0x0 DIS Disbale interrupt mask
0x1 EN Enable interrupt mask
RW 0

TOP:I2C0:TRIS

Address Offset 0x0000 0010
Physical Address 0x4003 8010 Instance 0x4003 8010
Description Target Raw Interrupt Status
This register shows the unmasked interrupt status.
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 STOPRIS Stop condition raw interrupt status
This bit is cleared by writing a 1 to SICR.STOPIC.
Value ENUM Name Description
0x0 CLEAR Interrupt did not occur
0x1 SET Interrupt occured
RO 0
1 STARTRIS Start condition raw interrupt status
This bit is cleared by writing a 1 to SICR.STARTIC.
Value ENUM Name Description
0x0 CLEAR Interrupt did not occur
0x1 SET Interrupt occured
RO 0
0 DATARIS Data raw interrupt status
This bit is cleared by writing a 1 to SICR.DATAIC.
Value ENUM Name Description
0x0 CLEAR Interrupt did not occur
0x1 SET Interrupt occured
RO 0

TOP:I2C0:TMIS

Address Offset 0x0000 0014
Physical Address 0x4003 8014 Instance 0x4003 8014
Description Target Masked Interrupt Status
This register show which interrupt is active (based on result from SRIS and SIMR).
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 STOPMIS Stop condition masked interrupt status
This bit is cleared by writing a 1 to SICR.STOPIC.
Value ENUM Name Description
0x0 CLEAR Masked interrupt did not occur
0x1 SET Masked interrupt occured
RO 0
1 STARTMIS Start condition masked interrupt status
This bit is cleared by writing a 1 to SICR.STARTIC.
Value ENUM Name Description
0x0 CLEAR Masked interrupt did not occur
0x1 SET Masked interrput occured
RO 0
0 DATAMIS Start condition masked interrupt status
This bit is cleared by writing a 1 to SICR.DATAIC.
Value ENUM Name Description
0x0 CLEAR Masked interrupt did not occur
0x1 SET Masked interrupt occured
RO 0

TOP:I2C0:TICR

Address Offset 0x0000 0018
Physical Address 0x4003 8018 Instance 0x4003 8018
Description Target Interrupt Clear
This register clears the raw interrupt SRIS.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 STOPIC Stop condition interrupt clear
Value ENUM Name Description
0x0 DIS No effect
0x1 EN Clear interrupt
Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.
WO 0
1 STARTIC Start condition interrupt clear
Value ENUM Name Description
0x0 DIS No effect
0x1 EN Clear interrupt
Writing 1 to this bit clears SRIS.STARTRIS and SMIS.STARTMIS.
WO 0
0 DATAIC Data interrupt clear
Value ENUM Name Description
0x0 DIS No effect
0x1 EN Clear interrupt
Writing 1 to this bit clears SRIS.DATARIS and SMIS.DATAMIS.
WO 0

TOP:I2C0:CSA

Address Offset 0x0000 0800
Physical Address 0x4003 8800 Instance 0x4003 8800
Description Controller Target Address
This register contains seven address bits of the target to be accessed by the controller (a6-a0), and an RS bit determining if the next operation is a receive or transmit.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:1 SA I2C controller target address
Defines which target is addressed for the transaction in controller mode		 RW 0b000 0000
0 RS Receive or Send
This bit-field specifies the next operation with addressed target SA.
Value ENUM Name Description
0x0 DIS Transmit/send data to target
0x1 EN Receive data from target
RW 0

TOP:I2C0:CSTAT_CTL

Address Offset 0x0000 0804
Physical Address 0x4003 8804 Instance 0x4003 8804
Description Controller Control and Status
This register functions as a control register when written, and a status register when read.
Type RW
Bits Field Name Description Type Reset
31:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000
6 BUSBSY Bus busy
Note:The bit changes based on the MCTRL.START and MCTRL.STOP conditions.
Value ENUM Name Description
0x0 CLEAR The I2C bus is idle.
0x1 SET The I2C bus is busy.
RO 0
5 IDLE This field specifies whether I2C is idle or not
Value ENUM Name Description
0x0 CLEAR The I2C controller is not idle.
0x1 SET The I2C controller is not idle.
RO 1
4 ARBLST The filed specifies the arbitration status
Value ENUM Name Description
0x0 CLEAR The I2C controller won arbitration.
0x1 SET The I2C controller lost arbitration.
RO 0
3 DATACKN_ACK This field contains Data acknowledge in status read and Data acknowledge enable in control write.
Status Read: Data Acknowledge
0 - The transmitted data was acknowledged.
1 - The transmitted data was not acknowledged.

Control write: Data acknowledge enable
0 - The received data byte is not acknowledged automatically by the controller.
1 - The received data byte is acknowledged automatically by the controller.
Note:This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the target transmitter.		 RW 0
2 ADRACKN_STOP This field reflects the address acknowledge status when read and sets stop condition when written.
When read:
0 - The transmitted address was acknowledged.
1 - The transmitted address was not acknowledged.

When written
Note:This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.
0 - The controller does not generate the Stop condition.
1 - The controller generates the Stop condition.		 RW 0
1 ERR_START This field reflect the error status when read and sets start or repeated start condition when written.
When read:
0 - No error was detected on the last operation.
1 - An error occurred on the last operation.

When written:
0 - The controller does not generate the Start condition.
1 - The controller generates the Start condition.		 RW 0
0 BUSY_RUN This field reflects the I2C busy status when read and sets I2C controller enable when written.
When Read
0 - The controller is idle.
1 - The controller is busy.

When this bit-field is set, the other status bits are not applicable.
Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C controller operation has been initiated through a write into MSTAT_MCTL register.
Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through a read from MSTAT_MCTL register. Any prior inquiry would result in wrong status being reported.

When written:
0 - The controller is disabled.
1 - The controller is enabled to transmit or receive data.		 RW 0

TOP:I2C0:CDR

Address Offset 0x0000 0808
Physical Address 0x4003 8808 Instance 0x4003 8808
Description Controller Data
This register contains the data to be transmitted when in the Controller Transmit state and the data received when in the Controller Receive state.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 DATA When Read: Last RX Data is returned
When Written: Data is transferred during TX transaction		 RW 0x00

TOP:I2C0:CTPR

Address Offset 0x0000 080C
Physical Address 0x4003 880C Instance 0x4003 880C
Description Controller Timer Period
This register specifies the period of the SCL clock.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 TPR_7 Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. RW 0
6:0 TPR SCL clock period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD, where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the timer period register value (range of 1 to 127)
SCL_LP is the SCL low period (fixed at 6).
SCL_HP is the SCL high period (fixed at 4).
CLK_PRD is the system clock period in ns.		 RW 0b000 0001

TOP:I2C0:CIMR

Address Offset 0x0000 0810
Physical Address 0x4003 8810 Instance 0x4003 8810
Description Controller Interrupt Mask
This register controls whether a raw interrupt is promoted to a controller interrupt.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 IM Interrupt mask
Value ENUM Name Description
0x0 DIS Disable Interrupt mask
0x1 EN Enable Interrupt mask
RW 0

TOP:I2C0:CRIS

Address Offset 0x0000 0814
Physical Address 0x4003 8814 Instance 0x4003 8814
Description Controller Raw Interrupt Status
This register show the unmasked interrupt status.
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 RIS Raw interrupt status
This bit is cleared by writing 1 to MICR.IC bit.
Value ENUM Name Description
0x0 CLEAR Interrupt did not occur
0x1 SET Interrupt occured
RO 0

TOP:I2C0:CMIS

Address Offset 0x0000 0818
Physical Address 0x4003 8818 Instance 0x4003 8818
Description Controller Masked Interrupt Status
This register show which interrupt is active (based on result from MRIS and MIMR).
Type RO
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 MIS Masked interrupt status
This bit is cleared by writing 1 to MICR.IC bit.
Value ENUM Name Description
0x0 CLEAR Masked interrupt did not occur
0x1 SET Masked interrupt occured
RO 0

TOP:I2C0:CICR

Address Offset 0x0000 081C
Physical Address 0x4003 881C Instance 0x4003 881C
Description Controller Interrupt Clear
This register clears the raw and masked interrupt.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 IC Interrupt clear
Value ENUM Name Description
0x0 DIS No effect
0x1 EN Clear Interrupt
Writing 1 to this bit clears MRIS.RIS and MMIS.MIS.
WO 0

TOP:I2C0:CCR

Address Offset 0x0000 0820
Physical Address 0x4003 8820 Instance 0x4003 8820
Description Controller Configuration
This register configures the mode (Controller or Target) and sets the interface for test mode loopback.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 SFE I2C target function enable
Value ENUM Name Description
0x0 DIS Target mode disabled
0x1 EN Target mode enabled
RW 0
4 MFE I2C controller function enable
Value ENUM Name Description
0x0 DIS Controller mode disabled
0x1 EN Controller mode enabled
RW 0
3:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
0 LPBK I2C loopback
Value ENUM Name Description
0x0 DIS Test mode (Loopback operation) disabled
0x1 EN Test mode (Loopback operation) enabled
RW 0


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