Instance: DCB
Component: DCB
Base address: 0xE000ED30
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 ED30 |
||
|
32 |
0x0000 0000 |
0x0000 00C0 |
0xE000 EDF0 |
||
|
32 |
0x0000 0000 |
0x0000 00C4 |
0xE000 EDF4 |
||
|
32 |
0x0000 0000 |
0x0000 00C8 |
0xE000 EDF8 |
||
|
32 |
0x0000 0000 |
0x0000 00CC |
0xE000 EDFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 ED30 | Instance | 0xE000 ED30 |
| Description | Use the Debug Fault Status Register to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution and BPU comparator matches, halt requests. Write one to clear. C_DEBUGEN must be set before any bits in DFSR are updated. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | EXTERNAL | External debug request flag 0x0:No edbgrq external debug request occurred 0x1:Edbgrq has halted the core |
RW | 0 | ||
| 3 | VCATCH | Vector catch flag. When the VCATCH flag is set, a flag in the Debug Exception and Monitor Control Register is also set to indicate the type of vector catch. 0x0:No vector catch occurred 0x1:Vector catch occurred |
RW | 0 | ||
| 2 | DWTRAP | Data Watchpoint (DW) flag. 0x0:No dw match 0x1:Dw match |
RW | 0 | ||
| 1 | BKPT | The BKPT flag is set by the execution of the BKPT instruction or on an instruction whose address triggered the breakpoint comparator match. When the processor has halted, the return PC points to the address of the breakpointed instruction. 0x0:No bkpt instruction or hardware breakpoint match 0x1:Bkpt instruction or hardware breakpoint match |
RW | 0 | ||
| 0 | HALTED | Halt request flag 0x0:No halt request 0x1:Halt requested by dap access to c_halt or halted with c_step asserted |
RW | 0 | ||
| Address Offset | 0x0000 00C0 | ||
| Physical Address | 0xE000 EDF0 | Instance | 0xE000 EDF0 |
| Description | The purpose of the Debug Halting Control and Status Register (DHCSR) is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to bits [31:16], otherwise the write operation is ignored and no bits are written into the register. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | |||||||||||
| 25 | S_RESET_ST | Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is currently reset and held in reset. | RO | 0 | |||||||||||
| 24 | S_RETIRE_ST | Core has retired at least part of an instruction since last read. This is a sticky bit that clears on read. | RO | 0 | |||||||||||
| 23:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | |||||||||||
| 17 | S_HALT | The core is halted in debug state only if S_HALT is set. | RO | 0 | |||||||||||
| 16 | S_REGRDY | Register Read/Write to the Debug Core Register Selector Register is available. Set in response to a successful register access. | RO | 0 | |||||||||||
| 15:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | |||||||||||
| 3 | C_MASKINTS | When this bit is set and debug is enabled, external interrupts, SysTick, and PendSV are masked. Does not affect NMI, Hard Fault or SVCall. When C_DEBUGEN = 0, this bit has no effect. | RW | 0 | |||||||||||
| 2 | C_STEP | Causes a debug event on any instruction or exception being executed, resulting in the core single stepping. | RW | 0 | |||||||||||
| 1 | C_HALT | Halts the core. This bit is set automatically when the core triggers a debug event, for example, on a breakpoint. This bit clears on core reset. When C_DEBUGEN = 0, this bit has no effect. | RW | 0 | |||||||||||
| 0 | C_DEBUGEN | Enables or disable debug
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 00C4 | ||
| Physical Address | 0xE000 EDF4 | Instance | 0xE000 EDF4 |
| Description | The purpose of the Debug Core Register Selector Register (DCRSR) is to select the processor register to transfer data to or from. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
| 16 | REGWnR | Register Write-not-Read 0x0:Read 0x1:Write |
WO | 0 | ||
| 15:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | ||
| 4:0 | REGSEL | Select processor register 0x00:R0 0x01:R1 0x02:R2 0x03:R3 0x04:R4 0x05:R5 0x06:R6 0x07:R7 0x08:R8 0x09:R9 0x0a:R10 0x0b:R11 0x0c:R12 0x0d:Current sp 0x0e:Lr 0x0f:Debugreturnaddress 0x10:Xpsr flags, execution number, and state information 0x11:Msp (main sp) 0x12:Psp (process sp) 0x14:Control (dcrdr[25:24]), primask (dcrdr[0]) |
WO | 0b0 0000 | ||
| Address Offset | 0x0000 00C8 | ||
| Physical Address | 0xE000 EDF8 | Instance | 0xE000 EDF8 |
| Description | The purpose of the Debug Core Register Data Register (DCRDR) is to hold data read from or written to core registers. | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | DBGTMP | Data temporary cache, for reading and writing registers. | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 00CC | ||
| Physical Address | 0xE000 EDFC | Instance | 0xE000 EDFC |
| Description | The purpose of the Debug Exception and Monitor Control Register (DEMCR) is: Global enable for the DW unit, Vector catching (that is, causes debug entry on execution of a specified vector.) | ||
| Type | |||
| Bits | Field Name | Description | Type | Reset | ||
| 31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 24 | DWTENA | Global enable or disable for the DW unit 0x0:Dw unit disabled. watchpoint cannot halt the core. the dw pcsr reads as oxffffffff. 0x1:Dw unit enabled |
RW | 0 | ||
| 23:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 | ||
| 10 | VC_HARDERR | Debug trap on a Hard Fault | RW | 0 | ||
| 9:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 0 | VC_CORERESET | Reset Vector Catch. Halt running system if HRESETn is asserted | RW | 0 | ||
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