Instance: ADC
Component: ADC
Base address: 0x40050000
ADC (Analog to Digital Converter) module
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4005 0028 |
|
RO |
32 |
0x0000 0000 |
0x0000 0030 |
0x4005 0030 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x4005 0038 |
|
WO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4005 0040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4005 0048 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x4005 0058 |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x4005 0060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4005 0068 |
|
WO |
32 |
0x0000 0000 |
0x0000 0070 |
0x4005 0070 |
|
WO |
32 |
0x0000 0000 |
0x0000 0078 |
0x4005 0078 |
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x4005 0088 |
|
RO |
32 |
0x0000 0000 |
0x0000 0090 |
0x4005 0090 |
|
RO |
32 |
0x0000 0000 |
0x0000 0098 |
0x4005 0098 |
|
WO |
32 |
0x0000 0000 |
0x0000 00A0 |
0x4005 00A0 |
|
WO |
32 |
0x0000 0000 |
0x0000 00A8 |
0x4005 00A8 |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4005 0100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0x4005 0104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4005 0108 |
|
RW |
32 |
0x0000 0000 |
0x0000 010C |
0x4005 010C |
|
RW |
32 |
0x0000 0000 |
0x0000 0114 |
0x4005 0114 |
|
RW |
32 |
0x0000 0000 |
0x0000 0118 |
0x4005 0118 |
|
RW |
32 |
0x0000 0000 |
0x0000 011C |
0x4005 011C |
|
RW |
32 |
0x0000 0000 |
0x0000 0148 |
0x4005 0148 |
|
RW |
32 |
0x0000 0000 |
0x0000 0150 |
0x4005 0150 |
|
RO |
32 |
0x0000 0000 |
0x0000 0160 |
0x4005 0160 |
|
RO |
32 |
0x0000 0000 |
0x0000 0170 |
0x4005 0170 |
|
RW |
32 |
0x0000 0000 |
0x0000 0180 |
0x4005 0180 |
|
RW |
32 |
0x0000 0000 |
0x0000 0184 |
0x4005 0184 |
|
RW |
32 |
0x0000 0000 |
0x0000 0188 |
0x4005 0188 |
|
RW |
32 |
0x0000 0000 |
0x0000 018C |
0x4005 018C |
|
RO |
32 |
0x0000 0000 |
0x0000 0280 |
0x4005 0280 |
|
RO |
32 |
0x0000 0000 |
0x0000 0284 |
0x4005 0284 |
|
RO |
32 |
0x0000 0000 |
0x0000 0288 |
0x4005 0288 |
|
RO |
32 |
0x0000 0000 |
0x0000 028C |
0x4005 028C |
|
RO |
32 |
0x0000 0000 |
0x0000 0340 |
0x4005 0340 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E00 |
0x4005 0E00 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E04 |
0x4005 0E04 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E08 |
0x4005 0E08 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E0C |
0x4005 0E0C |
|
RW |
32 |
0x0000 0000 |
0x0000 0E10 |
0x4005 0E10 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E14 |
0x4005 0E14 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E18 |
0x4005 0E18 |
|
RW |
32 |
0x0080 1000 |
0x0000 0E20 |
0x4005 0E20 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E24 |
0x4005 0E24 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E28 |
0x4005 0E28 |
|
RW |
32 |
0x0000 0000 |
0x0000 0E2C |
0x4005 0E2C |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4005 0028 | Instance | 0x4005 0028 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | MEMRES3 conversion result interrupt mask.
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | MEMRES2 conversion result interrupt mask.
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | MEMRES1 conversion result interrupt mask.
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | MEMRES0 conversion result interrupt mask.
|
RW | 0 | |||||||||||
7 | ASCDONE | Mask for ASC done raw interrupt flag
|
RW | 0 | |||||||||||
6 | UVIFG | Conversion underflow interrupt mask
|
RW | 0 | |||||||||||
5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
4 | INIFG | In-range comparator interrupt mask.
|
RW | 0 | |||||||||||
3 | LOWIFG | Low threshold compare interrupt mask
|
RW | 0 | |||||||||||
2 | HIGHIFG | High threshold compare interrupt mask
|
RW | 0 | |||||||||||
1 | TOVIFG | Sequence conversion time overflow interrupt mask
|
RW | 0 | |||||||||||
0 | OVIFG | Conversion overflow interrupt mask
|
RW | 0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4005 0030 | Instance | 0x4005 0030 |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7 | ASCDONE | Raw interrupt flag for ASC done
|
RW | 0 | |||||||||||
6 | UVIFG | Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
|
RW | 0 | |||||||||||
5 | DMADONE | Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1 | TOVIFG | Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
0 | OVIFG | Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4005 0038 | Instance | 0x4005 0038 |
Description | Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7 | ASCDONE | Masked interrupt status for ASC done
|
RW | 0 | |||||||||||
6 | UVIFG | Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.
|
RW | 0 | |||||||||||
5 | DMADONE | Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1 | TOVIFG | Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
0 | OVIFG | Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4005 0040 | Instance | 0x4005 0040 |
Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET0 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7 | ASCDONE | Set ASC done flag in RIS
|
RW | 0 | |||||||||||
6 | UVIFG | Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
5 | DMADONE | Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1 | TOVIFG | Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
0 | OVIFG | Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4005 0048 | Instance | 0x4005 0048 |
Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7 | ASCDONE | Clear ASC done flag in RIS
|
RW | 0 | |||||||||||
6 | UVIFG | Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
5 | DMADONE | Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1 | TOVIFG | Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
0 | OVIFG | Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4005 0058 | Instance | 0x4005 0058 |
Description | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4005 0060 | Instance | 0x4005 0060 |
Description | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS1 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4005 0068 | Instance | 0x4005 0068 |
Description | Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4005 0070 | Instance | 0x4005 0070 |
Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET1 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x4005 0078 | Instance | 0x4005 0078 |
Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
4 | INIFG | Mask INIFG in MIS_EX register.
|
RW | 0 | |||||||||||
3 | LOWIFG | Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
2 | HIGHIFG | Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.
|
RW | 0 | |||||||||||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 |
Address Offset | 0x0000 0088 | ||
Physical Address | 0x4005 0088 | Instance | 0x4005 0088 |
Description | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 0090 | ||
Physical Address | 0x4005 0090 | Instance | 0x4005 0090 |
Description | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS2 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 0098 | ||
Physical Address | 0x4005 0098 | Instance | 0x4005 0098 |
Description | Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x4005 00A0 | Instance | 0x4005 00A0 |
Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET2 will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 00A8 | ||
Physical Address | 0x4005 00A8 | Instance | 0x4005 00A8 |
Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
11 | MEMRESIFG3 | Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
10 | MEMRESIFG2 | Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
9 | MEMRESIFG1 | Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
8 | MEMRESIFG0 | Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1
|
RW | 0 | |||||||||||
7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4005 0100 | Instance | 0x4005 0100 |
Description | Control Register 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:27 | RESERVED27 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||||||||||||||
26:24 | SCLKDIV | Sample clock divider
|
RW | 0b000 | |||||||||||||||||||||||||||||
23:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||||||||||||||||||||
16 | PWRDN | Power down policy
|
RW | 0 | |||||||||||||||||||||||||||||
15:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | |||||||||||||||||||||||||||||
0 | ENC | Enable conversion
|
RW | 0 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4005 0104 | Instance | 0x4005 0104 |
Description | Control Register 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||||||||
20 | SAMPMODE | Sample mode. This bit selects the source of the sampling signal. MANUAL option is not applicable when TRIGSRC is selected as hardware event trigger.
|
RW | 0 | |||||||||||||||||
19:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||
17:16 | CONSEQ | Conversion sequence mode
|
RW | 0b00 | |||||||||||||||||
15:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||||||||
8 | SC | Start of conversion
|
RW | 0 | |||||||||||||||||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||||||||
0 | TRIGSRC | Sample trigger source
|
RW | 0 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4005 0108 | Instance | 0x4005 0108 |
Description | Control Register 2 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28:24 | ENDADD | Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20:16 | STARTADD | Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | FIFOEN | Enable FIFO based operation
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | DMAEN | Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2:1 | RES | Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | DF | Data read-back format. Data is always stored in binary unsigned format.
|
RW | 0 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4005 010C | Instance | 0x4005 010C |
Description | Control Register 3. This register is used to configure ADC for ad-hoc single conversion. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13:12 | ASCVRSEL | Selects voltage reference for ASC operation. AREF- must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ASCSTIME | ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | ASCCHSEL | ASC channel select
|
RW | 0b0 0000 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4005 0114 | Instance | 0x4005 0114 |
Description | Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 | ||
9:0 | VAL | Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. |
RW | 0b00 0000 0000 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4005 0118 | Instance | 0x4005 0118 |
Description | Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 | ||
9:0 | VAL | Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL > 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles. |
RW | 0b00 0000 0000 |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4005 011C | Instance | 0x4005 011C |
Description | Reference buffer configuration register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
4:3 | IBPROG | Configures reference buffer bias current output value
|
RW | 0b00 | |||||||||||||||||
2 | SPARE | Spare bit | RW | 0 | |||||||||||||||||
1 | REFVSEL | Configures reference buffer output voltage
|
RW | 0 | |||||||||||||||||
0 | REFEN | Reference buffer enable
|
RW | 0 |
Address Offset | 0x0000 0148 | ||
Physical Address | 0x4005 0148 | Instance | 0x4005 0148 |
Description | Window Comparator Low Threshold Register. The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCLOW. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s. |
RW | 0x0000 |
Address Offset | 0x0000 0150 | ||
Physical Address | 0x4005 0150 | Instance | 0x4005 0150 |
Description | Window Comparator High Threshold Register. The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register. CTL0.ENC must be 0 to write to this register. Note: Change in ADC data format or resolution does not reset WCHIGH. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s. |
RW | 0x0000 |
Address Offset | 0x0000 0160 | ||
Physical Address | 0x4005 0160 | Instance | 0x4005 0160 |
Description | FIFO data register. This is a virtual register used to do read from FIFO. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | DATA | Read from this data field returns the ADC sample from FIFO. | RW | 0x0000 0000 |
Address Offset | 0x0000 0170 | ||
Physical Address | 0x4005 0170 | Instance | 0x4005 0170 |
Description | ASC result register | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | Result of ADC ad-hoc single conversion. If DF = 0, unsigned binary: The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. |
RO | 0x0000 |
Address Offset | 0x0000 0180 | ||
Physical Address | 0x4005 0180 | Instance | 0x4005 0180 |
Description | Conversion Memory Control Register 0. CTL0.ENC must be set to 0 to write to this register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | WINCOMP | Enable window comparator.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | TRG | Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | STIME | Selects the source of sample timer period between SCOMP0 and SCOMP1.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:8 | VRSEL | Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | CHANSEL | Input channel select.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0184 | ||
Physical Address | 0x4005 0184 | Instance | 0x4005 0184 |
Description | Conversion Memory Control Register 1. CTL0.ENC must be set to 0 to write to this register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | WINCOMP | Enable window comparator.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | TRG | Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | STIME | Selects the source of sample timer period between SCOMP0 and SCOMP1.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:8 | VRSEL | Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | CHANSEL | Input channel select.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0188 | ||
Physical Address | 0x4005 0188 | Instance | 0x4005 0188 |
Description | Conversion Memory Control Register 2. CTL0.ENC must be set to 0 to write to this register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | WINCOMP | Enable window comparator.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | TRG | Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | STIME | Selects the source of sample timer period between SCOMP0 and SCOMP1.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:8 | VRSEL | Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | CHANSEL | Input channel select.
|
RW | 0b0 0000 |
Address Offset | 0x0000 018C | ||
Physical Address | 0x4005 018C | Instance | 0x4005 018C |
Description | Conversion Memory Control Register 3. CTL0.ENC must be set to 0 to write to this register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | WINCOMP | Enable window comparator.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | TRG | Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | STIME | Selects the source of sample timer period between SCOMP0 and SCOMP1.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:8 | VRSEL | Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.
|
RW | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | CHANSEL | Input channel select.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0280 | ||
Physical Address | 0x4005 0280 | Instance | 0x4005 0280 |
Description | Memory Result Register 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. |
RW | 0x0000 |
Address Offset | 0x0000 0284 | ||
Physical Address | 0x4005 0284 | Instance | 0x4005 0284 |
Description | Memory Result Register 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. |
RW | 0x0000 |
Address Offset | 0x0000 0288 | ||
Physical Address | 0x4005 0288 | Instance | 0x4005 0288 |
Description | Memory Result Register 2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. |
RW | 0x0000 |
Address Offset | 0x0000 028C | ||
Physical Address | 0x4005 028C | Instance | 0x4005 028C |
Description | Memory Result Register 3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back. |
RW | 0x0000 |
Address Offset | 0x0000 0340 | ||
Physical Address | 0x4005 0340 | Instance | 0x4005 0340 |
Description | Status Register | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
2 | ASCACT | ASC active
|
RO | 0 | |||||||||||
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
0 | BUSY | Busy. This bit indicates that an active ADC sample or conversion operation is in progress.
|
RO | 0 |
Address Offset | 0x0000 0E00 | ||
Physical Address | 0x4005 0E00 | Instance | 0x4005 0E00 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
31 | RESERVED31 | Internal. Only to be used through TI provided API. | RO | 0 | ||||||||||||||||||||
30 | ATEST0_EN | Internal. Only to be used through TI provided API.
|
RW | 0 | ||||||||||||||||||||
29 | ATEST1_EN | Internal. Only to be used through TI provided API.
|
RW | 0 | ||||||||||||||||||||
28:13 | RESERVED13 | Internal. Only to be used through TI provided API. | RO | 0x0000 | ||||||||||||||||||||
12:8 | ATEST1_MUXSEL | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 | ||||||||||||||||||||
7:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RO | 0b000 | ||||||||||||||||||||
4:0 | ATEST0_MUXSEL | Internal. Only to be used through TI provided API.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0E04 | ||
Physical Address | 0x4005 0E04 | Instance | 0x4005 0E04 |
Description | Test 1 register. This is used to select ADC internal signals on DTB. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
4:0 | DTB_MUXSEL | DTB mux select. | RW | 0b0 0000 |
Address Offset | 0x0000 0E08 | ||
Physical Address | 0x4005 0E08 | Instance | 0x4005 0E08 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31 | CDAC_OVST_EN | Internal. Only to be used through TI provided API. | RW | 0 | ||
30:25 | RESERVED25 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 | ||
24 | LATCH_TRIM_EN | Internal. Only to be used through TI provided API. | RW | 0 | ||
23:21 | RESERVED21 | Internal. Only to be used through TI provided API. | RO | 0b000 | ||
20 | COMP_GAIN_TRIM | Internal. Only to be used through TI provided API. | RW | 0 | ||
19:9 | RESERVED9 | Internal. Only to be used through TI provided API. | RO | 0b000 0000 0000 | ||
8 | MUX_TEST_SEL | Internal. Only to be used through TI provided API. | RW | 0 | ||
7:0 | RESERVED0 | Internal. Only to be used through TI provided API. | RO | 0x00 |
Address Offset | 0x0000 0E0C | ||
Physical Address | 0x4005 0E0C | Instance | 0x4005 0E0C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | CAL_ACUML | Internal. Only to be used through TI provided API. | RW | 0x0000 0000 |
Address Offset | 0x0000 0E10 | ||
Physical Address | 0x4005 0E10 | Instance | 0x4005 0E10 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31 | HW_STEP_SEL_DIS | Internal. Only to be used through TI provided API. | RW | 0 | ||
30:25 | RESERVED25 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 | ||
24 | CAL_MODE_EN | Internal. Only to be used through TI provided API. | RW | 0 | ||
23:22 | RESERVED22 | Internal. Only to be used through TI provided API. | RO | 0b00 | ||
21:16 | CAL_STEP_SEL | Internal. Only to be used through TI provided API. | RW | 0b00 0000 | ||
15:0 | RESERVED0 | Internal. Only to be used through TI provided API. | RO | 0x0000 |
Address Offset | 0x0000 0E14 | ||
Physical Address | 0x4005 0E14 | Instance | 0x4005 0E14 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:10 | RESERVED10 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 | ||
9:0 | CAL_CAP_CTL | Internal. Only to be used through TI provided API. | RW | 0b00 0000 0000 |
Address Offset | 0x0000 0E18 | ||
Physical Address | 0x4005 0E18 | Instance | 0x4005 0E18 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
31:4 | RESERVED4 | Internal. Only to be used through TI provided API. | RO | 0x000 0000 | ||||||||||||||||||||
3:0 | ATESTSEL | Internal. Only to be used through TI provided API.
|
RW | 0x0 |
Address Offset | 0x0000 0E20 | ||
Physical Address | 0x4005 0E20 | Instance | 0x4005 0E20 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | CTRL | Internal. Only to be used through TI provided API. | RW | 0x0080 1000 |
Address Offset | 0x0000 0E24 | ||
Physical Address | 0x4005 0E24 | Instance | 0x4005 0E24 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:30 | RESERVED30 | Internal. Only to be used through TI provided API. | RO | 0b00 | ||
29:28 | VTOI_CTRL | Internal. Only to be used through TI provided API. | RW | 0b00 | ||
27:25 | RESERVED25 | Internal. Only to be used through TI provided API. | RO | 0b000 | ||
24 | VTOI_TESTMODE_EN | Internal. Only to be used through TI provided API. | RW | 0 | ||
23:0 | RESERVED0 | Internal. Only to be used through TI provided API. | RO | 0x00 0000 |
Address Offset | 0x0000 0E28 | ||
Physical Address | 0x4005 0E28 | Instance | 0x4005 0E28 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Internal. Only to be used through TI provided API. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
5 | DEC1_DIS | Internal. Only to be used through TI provided API. | RW | 0 | ||
4 | DEC0_DIS | Internal. Only to be used through TI provided API. | RW | 0 | ||
3:1 | RESERVED1 | Internal. Only to be used through TI provided API. | RO | 0b000 | ||
0 | BOOST_ENZ | Internal. Only to be used through TI provided API. | RW | 0 |
Address Offset | 0x0000 0E2C | ||
Physical Address | 0x4005 0E2C | Instance | 0x4005 0E2C |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Internal. Only to be used through TI provided API. | RO | 0x0000 | ||
15:0 | ADC_CTRL0 | Internal. Only to be used through TI provided API. | RW | 0x0000 |
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