CC26xx Driver Library
Macros | Functions
setup.c File Reference
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_adi.h"
#include "../inc/hw_adi_2_refsys.h"
#include "../inc/hw_adi_3_refsys.h"
#include "../inc/hw_adi_4_aux.h"
#include "../inc/hw_aon_ioc.h"
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_aon_rtc.h"
#include "../inc/hw_ddi_0_osc.h"
#include "../inc/hw_ddi.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_flash.h"
#include "../inc/hw_prcm.h"
#include "../inc/hw_vims.h"
#include "aux_sysif.h"
#include "chipinfo.h"
#include "setup.h"
#include "setup_rom.h"

Macros

#define ADI_4_AUX_O_LPMBIAS   0x0000000E
 
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M   0x0000003F
 
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S   0
 
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M   0x00000038
 
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S   3
 
#define CPU_DELAY_MICRO_SECONDS(x)   CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
 

Functions

static void TrimAfterColdReset (void)
 Trims to be applied when coming from PIN_RESET. More...
 
static void TrimAfterColdResetWakeupFromShutDown (uint32_t ui32Fcfg1Revision)
 Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET). More...
 
static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown (void)
 Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET). More...
 
void SetupTrimDevice (void)
 Performs the necessary trim of the device which is not done in boot code. More...
 
static void Step_RCOSCHF_CTRIM (uint32_t toCode)
 
static void Step_VBG (int32_t targetSigned)
 

Macro Definition Documentation

#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M   0x00000038

Referenced by TrimAfterColdResetWakeupFromShutDown().

#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S   3

Referenced by TrimAfterColdResetWakeupFromShutDown().

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M   0x0000003F

Referenced by TrimAfterColdResetWakeupFromShutDown().

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S   0

Referenced by TrimAfterColdResetWakeupFromShutDown().

#define ADI_4_AUX_O_LPMBIAS   0x0000000E

Referenced by TrimAfterColdResetWakeupFromShutDown().

#define CPU_DELAY_MICRO_SECONDS (   x)    CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )

Function Documentation

static void Step_RCOSCHF_CTRIM ( uint32_t  toCode)
static

Referenced by TrimAfterColdResetWakeupFromShutDown().

235 {
236  uint32_t currentRcoscHfCtlReg ;
237  uint32_t currentTrim ;
238 
239  currentRcoscHfCtlReg = HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL );
240  currentTrim = ((( currentRcoscHfCtlReg & DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) >>
241  DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S ) ^ 0xC0 );
242 
243  while ( toCode != currentTrim ) {
244  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
245 
246  if ( toCode > currentTrim ) currentTrim++;
247  else currentTrim--;
248 
249  HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL ) =
250  ( currentRcoscHfCtlReg & ~DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) |
251  (( currentTrim ^ 0xC0 ) << DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S );
252  }
253 }
static void Step_VBG ( int32_t  targetSigned)
static

Referenced by TrimAfterColdResetWakeupFromShutDown().

257 {
258  // VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG)
259  uint32_t refSysCtl3Reg ;
260  int32_t currentSigned ;
261 
262  do {
263  refSysCtl3Reg = HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 );
264  currentSigned =
265  (((int32_t)( refSysCtl3Reg << ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S )))
266  >> ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W ));
267 
268  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
269 
270  if ( targetSigned != currentSigned ) {
271  if ( targetSigned > currentSigned ) currentSigned++;
272  else currentSigned--;
273 
274  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) =
275  ( refSysCtl3Reg & ~( ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN | ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M )) |
276  ((((uint32_t)currentSigned) << ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S ) & ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M );
277 
278  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write
279  }
280  } while ( targetSigned != currentSigned );
281 }
static void TrimAfterColdReset ( void  )
static

Trims to be applied when coming from PIN_RESET.

Returns
None

Referenced by SetupTrimDevice().

478 {
479  // Currently no specific trim for Cold Reset
480 }
static void TrimAfterColdResetWakeupFromShutDown ( uint32_t  ui32Fcfg1Revision)
static

Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).

Parameters
ui32Fcfg1Revision
Returns
None

Referenced by SetupTrimDevice().

295 {
296  uint32_t ccfg_ModeConfReg ;
297 
298  // Check in CCFG for alternative DCDC setting
299  if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
300  // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN)
301  // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK )
302  // Using a single 4-bit masked write since layout is equal for both source and destination
303  HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
304  ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
305 
306  }
307 
308  // TBD - Temporarily removed for CC13x2 / CC26x2
309 
310  // Force DCDC to use RCOSC before starting up XOSC.
311  // Clock loss detector does not use XOSC until SCLK_HF actually switches
312  // and thus DCDC is not protected from clock loss on XOSC in that time frame.
313  // The force must be released when the switch to XOSC has happened. This is done
314  // in OSCHfSourceSwitch().
315  HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
316  // Dummy read to ensure that the write has propagated
317  HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
318 
319  // read the MODE_CONF register in CCFG
320  ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
321 
322  // First part of trim done after cold reset and wakeup from shutdown:
323  // -Adjust the VDDR_TRIM_SLEEP value.
324  // -Configure DCDC.
325  SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );
326 
327  // Second part of trim done after cold reset and wakeup from shutdown:
328  // -Configure XOSC.
329 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
330  SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
331 #else
332  NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
333 #endif
334 
335  // Special shadow register trim propagation on first batch of devices
336  {
337  uint32_t ui32EfuseData ;
338  uint32_t orgResetCtl ;
339 
340  // Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register OSC_BIAS_LDO_TRIM
341  ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM );
342 
343  Step_RCOSCHF_CTRIM(( ui32EfuseData &
344  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M ) >>
345  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S ) ;
346 
347  // Write to register SOCLDO_0_1 (addr offset 3) bits[7:4] (VTRIM_COARSE) and
348  // bits[3:0] (VTRIM_DIG) in ADI_2_REFSYS. Direct write can be used since
349  // all register bit fields are trimmed.
350  HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_SOCLDOCTL1) =
351  ((((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M) >>
352  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S) <<
353  ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S) |
354 
355  (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M) >>
356  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S) <<
357  ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S));
358 
359  // Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
360  // ADI_2_REFSYS. Avoid using masked write access since bit field spans
361  // nibble boundary. Direct write can be used since this is the only defined
362  // bit field in this register.
363  HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_REFSYSCTL0) =
364  (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M) >>
365  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S) <<
366  ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S);
367 
368  // Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
369  // ADI_3_REFSYS
370  HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL2 << 1)) =
371  (ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M << 8) |
372  (((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M) >>
373  FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S) <<
374  ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S);
375 
376  // Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in FCFG1
377  ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM );
378 
379  orgResetCtl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
380  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) =
381  ( orgResetCtl & ~( AON_PMCTL_RESETCTL_CLK_LOSS_EN |
382  AON_PMCTL_RESETCTL_VDD_LOSS_EN |
383  AON_PMCTL_RESETCTL_VDDR_LOSS_EN |
384  AON_PMCTL_RESETCTL_VDDS_LOSS_EN ));
385  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate
386 
387  // The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if "CC1352 boost mode" is requested.
388  // See function SetupAfterColdResetWakeupFromShutDownCfg1() in setup_rom.c for details.
389  if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) != 0 ) ||
390  (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) == 0 ) )
391  {
392  if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
393  AON_PMCTL_PWRCTL_EXT_REG_MODE)
394  {
395  // Apply VDDS BOD trim value
396  // Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD)
397  // in ADI_3_REFSYS
398  HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
399  (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
400  (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M) >>
401  FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S) <<
402  ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
403  }
404  else
405  {
406  // Apply VDDS BOD trim value
407  // Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD)
408  // in ADI_3_REFSYS
409  HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
410  (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
411  (((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M) >>
412  FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S) <<
413  ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
414  }
415  // Load the new VDDS_BOD setting
416  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit clear by doing a read modify write
417  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write
418 
419  SetupStepVddrTrimTo(( ui32EfuseData &
420  FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
421  FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ;
422  }
423 
424  // VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG)
425  Step_VBG(((int32_t)( ui32EfuseData << ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S )))
426  >> ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W ));
427 
428  // Wait two more LF edges before restoring xxx_LOSS_EN settings
429  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
430  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
431  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = orgResetCtl;
432  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate
433  }
434 
435  {
436  uint32_t trimReg ;
437  uint32_t ui32TrimValue ;
438 
439  //--- Propagate the LPM_BIAS trim ---
440  trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF );
441  ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >>
442  FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
443  HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) &
444  ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ;
445  //--- Set fixed LPM_BIAS values --- LPM_BIAS_BACKUP_EN = 1 and LPM_BIAS_WIDTH_TRIM = 3
446  HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
447  HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
448  (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8]
449  ( 3 << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0]
450  }
451 
452  // Third part of trim done after cold reset and wakeup from shutdown:
453  // -Configure HPOSC.
454  // -Setup the LF clock.
455 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
456  SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
457 #else
458  NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
459 #endif
460 
461  // Set AUX into power down active mode
462  AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA );
463 
464  // Disable EFUSE clock
465  HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
466 }
Step_VBG
static void Step_VBG(int32_t targetSigned)
Definition: setup.c:256
ADI_4_AUX_O_LPMBIAS
#define ADI_4_AUX_O_LPMBIAS
Definition: setup.c:47
SetupAfterColdResetWakeupFromShutDownCfg3
void SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg)
Third part of configuration required when waking up from shutdown.
Definition: setup_rom.c:324
ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S
Definition: setup.c:51
ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M
Definition: setup.c:50
AUX_SYSIF_OPMODE_TARGET_PDA
#define AUX_SYSIF_OPMODE_TARGET_PDA
Definition: aux_sysif.h:99
SetupAfterColdResetWakeupFromShutDownCfg1
void SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg)
First part of configuration required when waking up from shutdown.
Definition: setup_rom.c:167
AUXSYSIFOpModeChange
void AUXSYSIFOpModeChange(uint32_t targetOpMode)
Changes the AUX operational mode to the requested target mode.
Definition: aux_sysif.c:67
ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S
Definition: setup.c:49
Step_RCOSCHF_CTRIM
static void Step_RCOSCHF_CTRIM(uint32_t toCode)
Definition: setup.c:234
SetupStepVddrTrimTo
void SetupStepVddrTrimTo(uint32_t toCode)
Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max) ...
Definition: setup_rom.c:119
SetupAfterColdResetWakeupFromShutDownCfg2
void SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)
Second part of configuration required when waking up from shutdown.
Definition: setup_rom.c:222
ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M
Definition: setup.c:48

Here is the call graph for this function:

static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown ( void  )
static

Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET).

Returns
None

Referenced by SetupTrimDevice().

227 {
228  // Currently no specific trim for Powerdown
229 }