UART2CC26X2 Hardware attributes. More...

#include <UART2CC26X2.h>

Data Fields
UART2_BASE_HWATTRS volatile tDMAControlTable *	dmaTxTableEntryPri

volatile tDMAControlTable *	dmaRxTableEntryPri

uint32_t	txChannelMask

uint32_t	rxChannelMask

PowerCC26XX_Resource	powerId

int32_t	txPinMux

int32_t	rxPinMux

int32_t	ctsPinMux

int32_t	rtsPinMux

UART2CC26X2_FifoThreshold	txIntFifoThr

UART2CC26X2_FifoThreshold	rxIntFifoThr

Detailed Description

UART2CC26X2 Hardware attributes.

The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

inc/hw_memmap.h
inc/hw_ints.h
driverlib/uart.h

intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). The CC26x2 uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).

  (7 << 5) will apply the lowest priority.
  (1 << 5) will apply the highest priority.

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2CC26X2_HWAttrs uartCC26X2HWAttrs[] = {
    {
        .baseAddr     = UARTA0_BASE,
        .intNum       = INT_UART0_COMB,
        .intPriority  = (~0),
        .flowControl  = UART2_FLOWCTRL_NONE,
        .rxPin        = IOID_2,
        .txPin        = IOID_3,
        .ctsPin       = GPIO_INVALID_INDEX,
        .rtsPin       = GPIO_INVALID_INDEX,
        .rxChannelMask  = 1 << UDMA_CHAN_UART0_RX,
        .txChannelMask  = 1 << UDMA_CHAN_UART0_TX,
        .txIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_1_8,
        .rxIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_4_8,
    },
    {
        .baseAddr     = UART1_BASE,
        .intNum       = INT_UART1_COMB,
        .intPriority  = (~0),
        .flowControl  = UART2_FLOWCTRL_NONE,
        .rxPin        = GPIO_INVALID_INDEX,
        .txPin        = GPIO_INVALID_INDEX,
        .ctsPin       = GPIO_INVALID_INDEX,
        .rtsPin       = GPIO_INVALID_INDEX,
        .rxChannelMask  = 1 << UDMA_CHAN_UART1_RX,
        .txChannelMask  = 1 << UDMA_CHAN_UART1_TX,
        .txIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_1_8,
        .rxIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_4_8,
    },
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE.

Field Documentation

§ dmaTxTableEntryPri

UART2_BASE_HWATTRS volatile tDMAControlTable* UART2CC26X2_HWAttrs::dmaTxTableEntryPri

uDMA controlTable primary TX entry

§ dmaRxTableEntryPri

volatile tDMAControlTable* UART2CC26X2_HWAttrs::dmaRxTableEntryPri

uDMA controlTable primary RX entry

§ txChannelMask

uint32_t UART2CC26X2_HWAttrs::txChannelMask

Mask for uDMA TX channel number (1 << channel number)

§ rxChannelMask

uint32_t UART2CC26X2_HWAttrs::rxChannelMask

Mask for uDMA RX channel number (1 << channel number)

§ powerId

PowerCC26XX_Resource UART2CC26X2_HWAttrs::powerId

Power driver ID of the UART instance

§ txPinMux

int32_t UART2CC26X2_HWAttrs::txPinMux

TX PIN mux value

§ rxPinMux

int32_t UART2CC26X2_HWAttrs::rxPinMux

RX PIN mux value

§ ctsPinMux

int32_t UART2CC26X2_HWAttrs::ctsPinMux

CTS PIN mux value for flow control

§ rtsPinMux

int32_t UART2CC26X2_HWAttrs::rtsPinMux

RTS PIN mux value for flow control

§ txIntFifoThr

UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::txIntFifoThr

UART TX interrupt FIFO threshold select

§ rxIntFifoThr

UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::rxIntFifoThr

UART RX interrupt FIFO threshold select

The documentation for this struct was generated from the following file:

UART2CC26X2.h

Data Fields