[aux_dac.h] AUX Digital to Analog Converter

Functions
void	AUXDACSetVref (uint8_t refSource)
	Sets the voltage reference source. More...
void	AUXDACEnablePreCharge (void)
	Enables DAC precharge. More...
void	AUXDACDisablePreCharge (void)
	Disables DAC precharge. More...
uint32_t	AUXDACCalcMax (void)
	Calculates the upper limit voltage the DAC can output. More...
uint32_t	AUXDACCalcMin (void)
	Calculates the lower limit voltage the DAC can output. More...
uint32_t	AUXDACCalcCode (uint32_t uVoltOut, uint32_t uVoltOutMin, uint32_t uVoltOutMax)
	Calculates the appropriate DAC code for a specific voltage value. More...
void	AUXDACSetSampleClock (uint8_t dacClkDiv)
	Configures and sets the DAC sample clock. More...
void	AUXDACSetCode (uint8_t dacCode)
	Updates the current DAC code. More...
void	AUXDACEnable (uint8_t dacPinId)
	Enables the DAC. More...
void	AUXDACDisable (void)
	Disables the DAC. More...

Detailed Description

Function Documentation

AUXDACCalcCode()

uint32_t AUXDACCalcCode	(	uint32_t	uVoltOut,
		uint32_t	uVoltOutMin,
		uint32_t	uVoltOutMax
	)

Calculates the appropriate DAC code for a specific voltage value.

Once a voltage reference source has been selected with AUXDACSetVref and the DAC's output voltage range has been defined with AUXDACCalcMin and AUXDACCalcMax, a DAC code can be derived.

Parameters

uVoltOut	The desired output voltage in millivolts [mV].
uVoltOutMin	The minimum output voltage in millivolts [mV] which can be output by the DAC in the current configuration. It should be the value returned by AUXDACCalcMin.
uVoltOutMax	The maximum output voltage in millivolts [mV] which can be output by the DAC in the current configuration. It should be the value returned by AUXDACCalcMax.

Returns

The dac code corresponding to the desired output value.

{
    uint32_t dacCode = 0;

    if(uVoltOut != 0)
    {
        // Rounding (by adding 0.5 before truncating)
        dacCode = (((254 * (uVoltOut - uVoltOutMin) * 2) / (uVoltOutMax - uVoltOutMin) + 1) / 2) + 1;
    }
    return (uint32_t)dacCode;
}

AUXDACCalcMax()

uint32_t AUXDACCalcMax

(

void

)

Calculates the upper limit voltage the DAC can output.

This function uses calibration coefficients stored in the factory configuration area (FCFG1) to determine the DAC's output voltage that corresponds to DAC code 255. This voltage depends on the selected voltage reference source.

Note

This function must only be called after AUXDACSetVref has been called.

Returns

The maximum voltage in mV that the DAC can output given a specific reference voltage.

{
    uint32_t prechargeStatus;
    uint32_t refSource;
    uint32_t dacMax;

    // Depending on the selected DAC voltage reference, obtain calibration value C2 in millivolts.
    refSource = ((HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) & ADI_4_AUX_MUX2_DAC_VREF_SEL_M) >> ADI_4_AUX_MUX2_DAC_VREF_SEL_S);

    switch (refSource)
    {
        // Nothing connected. Input is floating.
        case AUXDAC_VREF_SEL_NC:

            dacMax = 0;
            break;

        // Core Voltage Decoupling pin as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_DCOUPL:

            prechargeStatus = ((HWREG( AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) & AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M) >> AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S);
            dacMax = (prechargeStatus == 0) ? ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL0) & FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M) >> FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S) \
                                            : ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL1) & FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M) >> FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S);
            break;

        // ADC reference voltage as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_ADCREF:

            dacMax = ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL2) & FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M) >> FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S);
            break;

        // Main supply voltage VDDS as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_VDDS:

            // Note: The calibration value is measured at a VDDS of 3.0V. If VDDS is selected as reference,
            // measure VDDS and scale the calibration value.
            dacMax = ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL3) & FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M) >> FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S);
            break;

        // Nothing connected. Input is floating.
        default:

            dacMax = 0;
    }

    return dacMax;
}

AUXDACCalcMin()

uint32_t AUXDACCalcMin

(

void

)

Calculates the lower limit voltage the DAC can output.

This function uses calibration coefficients stored in the factory configuration area (FCFG1) to determine the DAC's output voltage that corresponds to DAC code 1. This voltage depends on the selected voltage reference source.

DAC Code 0 corresponds to 0 V. Therefore, the DAC can only output 0 V and values between the lower limit defined by this function and the upper limit defined by AUXDACCalcMax.

Note

This function must only be called after AUXDACSetVref has been called.

Returns

The minimum voltage (other than 0 V) in mV that the DAC can output given a specific reference voltage.

{
    uint32_t refSource;
    uint32_t prechargeStatus;
    uint32_t dacMin;

    // Depending on the selected DAC voltage reference, obtain calibration value C1 in millivolts.
    refSource = ((HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) & ADI_4_AUX_MUX2_DAC_VREF_SEL_M) >> ADI_4_AUX_MUX2_DAC_VREF_SEL_S);

    switch (refSource)
    {
        // Nothing connected. Input is floating.
        case AUXDAC_VREF_SEL_NC:
            dacMin = 0;
            break;

        // Core Voltage Decoupling pin as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_DCOUPL:

            prechargeStatus = ((HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) & AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M) >> AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S);
            dacMin = (prechargeStatus == 0) ? ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL0) & FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M) >> FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S) \
                                            : ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL1) & FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M) >> FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S);
            break;

        // ADC reference voltage as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_ADCREF:
            dacMin = ((HWREG( FCFG1_BASE + FCFG1_O_DAC_CAL2) & FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M) >> FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S);
            break;

        // Main supply voltage VDDS as the DAC's voltage reference source.
        case AUXDAC_VREF_SEL_VDDS:
            dacMin = ((HWREG( FCFG1_BASE + FCFG1_O_DAC_CAL3) & FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M) >> FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S);
            break;

        // Nothing connected. Input is floating.
        default:

            dacMin = 0;
    }

    return dacMin;
}

AUXDACDisable()

void AUXDACDisable

(

void

)

Disables the DAC.

This function disables the DAC sample clock, the DAC buffer, the DAC. It also disconnects COMPA_IN internally.

Note

This function must be called only after AUXDACEnable has been called.

{
    // Disable the DAC sample clock
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCTL) = 0x0;

    // Disable DAC, the DAC's buffer, and disconnect internally.
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) &= ~(0x1 << AUX_ANAIF_DACCTL_DAC_EN_S) &      \
                                                   ~(0x1 << AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S) &   \
                                                   ~(AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M << AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S);

    // Disconnect COMPA_IN from DIOs
    HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX1) = 0x0;

    // Set operational mode to Power-Down
    HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = AUX_SYSIF_OPMODEREQ_REQ_PDA;

    // Set the peripheral operational rate to the SCE rate
    HWREGB(AUX_SYSIF_BASE + AUX_SYSIF_O_PEROPRATE) = AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE;
}

AUXDACDisablePreCharge()

void AUXDACDisablePreCharge

(

void

)

Disables DAC precharge.

If AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference source, the DAC's output voltage range can be further controlled by enabling or disabling precharge.

When precharge is disabled the DAC's output voltage will range from 0 V to 1.28 V.

Note

This function must only be called if AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference source and while the DAC is disabled, before calling AUXDACEnable().

{
    HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) &= ~(0x1 << AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S);
}

AUXDACEnable()

void AUXDACEnable

(

uint8_t

dacPinId

)

Enables the DAC.

This function enables the DAC sample clock and the DAC buffer. It selects COMPA_IN as output, and it routes the DAC's output to the given I/O pin.

Parameters

dacPinId

Analog capable I/O pin: AUXDAC_COMPA_IN_AUXIO26 AUXDAC_COMPA_IN_AUXIO25 AUXDAC_COMPA_IN_AUXIO24 AUXDAC_COMPA_IN_AUXIO23 AUXDAC_COMPA_IN_AUXIO22 AUXDAC_COMPA_IN_AUXIO21 AUXDAC_COMPA_IN_AUXIO20 AUXDAC_COMPA_IN_AUXIO19

{
    // Set the operational mode to active
    HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = AUX_SYSIF_OPMODEREQ_REQ_A;

    // Disable the low power bias control
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_LPMBIASCTL) = 0x0;

    // Enable the DAC sample clock
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCTL) = AUX_ANAIF_DACSMPLCTL_EN;

    // Enable DAC and buffer and set COMPA_IN
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) |= AUX_ANAIF_DACCTL_DAC_EN | AUX_ANAIF_DACCTL_DAC_BUFFER_EN | AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN;

    // Select COMPA output (0 will disconnect from DIOs)
    HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX1) = dacPinId;
}

AUXDACEnablePreCharge()

void AUXDACEnablePreCharge

(

void

)

Enables DAC precharge.

If AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference source, the DAC's output voltage range can be further controlled by enabling or disabling precharge.

When precharge is enabled the DAC's output voltage will range from 1.28 V to 2.56 V.

Note

This function must only be called if AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference source and while the DAC is disabled, before calling AUXDACEnable().

{
    HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) |= AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN;
}

AUXDACSetCode()

void AUXDACSetCode

(

uint8_t

dacCode

)

Updates the current DAC code.

This function is meant to be used after AUXDACEnable has been called. It allows to update the DAC code by rapidly disabling the DAC, setting the new DAC code, and then rapidly re-enabling the DAC.

Parameters

dacCode

The new DAC code

{
    // Update the DAC's output value.
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACVALUE) = dacCode;
}

AUXDACSetSampleClock()

void AUXDACSetSampleClock

(

uint8_t

dacClkDiv

)

Configures and sets the DAC sample clock.

This function determines the sample clock frequency assuming that the operational rate for the DAC sample clock state machine is the AUX Bus Rate. AUX Bus frequency (24 MHz) divided by (dacClkDiv + 1) determines the sample base clock frequency(SBCLK).

In this implementation, the high and low hold period (H_PER and L_PER) are both set to 4 periods, resulting in a DAC sample clock of SBCLK/8.

The formula (24 MHz / (dacCLKDiv +1)) / 8 describes the final DAC Sample Clock Frequency. For example, dacCLKDiv = 11 gives SBCLK frequency = 24 MHz / (11+1) = 2 MHz, which gives DAC sample clock frequency = 2 MHz / 8 = 250 KHz.

Note

The max sample clock frequency supported by the DAC is 1 MHz for internal load and 250 kHz for external load. The current implementation of the DAC driver assumes that it will be used to drive an internal load. Please refer to the register description before changing sample clock configuration settings. The DAC may behave unexpectedly if the sample clock operates at unsupported frequencies.

This function must be called before AUXDACEnable.

Parameters

dacClkDiv

The clock division factor

{

    // Set the peripheral operational rate to the AUX bus rate of 24 MHz.
    HWREGB(AUX_SYSIF_BASE + AUX_SYSIF_O_PEROPRATE) |= AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE;

    // Configure sample base clock (SBCLK). SBCLK = 24 MHz / (dacClkDiv + 1).
    // Max possible dacCLKDiv value = 63.
    HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCFG0) = dacClkDiv;

    // Configure DAC sample clock:
    //
    // - Set 16 active sample clock periods during setup phase.
    // - Set 0 inactive sample clock periods between each active sample clock
    //    period during hold phase.
    // - Set high and low hold period to 4, resulting in a DAC sample clock of
    //    SBCLK/8.
    //
    // This makes DAC clock frequency = (24 MHz / (dacCLKDiv + 1)) / 8

    HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCFG1) = (SAMPLE_CLK_HOLD_PERIOD)|
                                                      (SAMPLE_CLK_SETUP_COUNT)|
                                                      (SAMPLE_CLK_LOW_PERIOD)|
                                                      (SAMPLE_CLK_HIGH_PERIOD);
}

AUXDACSetVref()

void AUXDACSetVref

(

uint8_t

refSource

)

Sets the voltage reference source.

The DAC's output range depends on the selection of a voltage reference source. This function must be called before enabling the DAC using AUXDACEnable() or before setting a DAC code using AUXDACCalcCode().

Parameters

refSource

DAC voltage reference source: AUXDAC_VREF_SEL_VDDS AUXDAC_VREF_SEL_ADCREF AUXDAC_VREF_SEL_DCOUPL AUXDAC_VREF_SEL_NC

{
    HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) = refSource;

    if(refSource == AUXDAC_VREF_SEL_ADCREF)
    {
        // Enable the ADC reference module.
        HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF0) |= ADI_4_AUX_ADCREF0_REF_ON_IDLE | ADI_4_AUX_ADCREF0_EN;
    }
}

Macro Definition Documentation

AUXDAC_COMPA_IN_AUXIO0

#define AUXDAC_COMPA_IN_AUXIO0   AUXDAC_COMPA_IN_AUXIO19

AUXDAC_COMPA_IN_AUXIO1

#define AUXDAC_COMPA_IN_AUXIO1   AUXDAC_COMPA_IN_AUXIO20

AUXDAC_COMPA_IN_AUXIO19

#define AUXDAC_COMPA_IN_AUXIO19   0x80

AUXDAC_COMPA_IN_AUXIO2

#define AUXDAC_COMPA_IN_AUXIO2   AUXDAC_COMPA_IN_AUXIO21

AUXDAC_COMPA_IN_AUXIO20

#define AUXDAC_COMPA_IN_AUXIO20   0x40

AUXDAC_COMPA_IN_AUXIO21

#define AUXDAC_COMPA_IN_AUXIO21   0x20

AUXDAC_COMPA_IN_AUXIO22

#define AUXDAC_COMPA_IN_AUXIO22   0x10

AUXDAC_COMPA_IN_AUXIO23

#define AUXDAC_COMPA_IN_AUXIO23   0x08

AUXDAC_COMPA_IN_AUXIO24

#define AUXDAC_COMPA_IN_AUXIO24   0x04

AUXDAC_COMPA_IN_AUXIO25

#define AUXDAC_COMPA_IN_AUXIO25   0x02

AUXDAC_COMPA_IN_AUXIO26

#define AUXDAC_COMPA_IN_AUXIO26   0x01

AUXDAC_COMPA_IN_AUXIO3

#define AUXDAC_COMPA_IN_AUXIO3   AUXDAC_COMPA_IN_AUXIO22

AUXDAC_COMPA_IN_AUXIO4

#define AUXDAC_COMPA_IN_AUXIO4   AUXDAC_COMPA_IN_AUXIO23

AUXDAC_COMPA_IN_AUXIO5

#define AUXDAC_COMPA_IN_AUXIO5   AUXDAC_COMPA_IN_AUXIO24

AUXDAC_COMPA_IN_AUXIO6

#define AUXDAC_COMPA_IN_AUXIO6   AUXDAC_COMPA_IN_AUXIO25

AUXDAC_COMPA_IN_AUXIO7

#define AUXDAC_COMPA_IN_AUXIO7   AUXDAC_COMPA_IN_AUXIO26

AUXDAC_COMPA_IN_NC

#define AUXDAC_COMPA_IN_NC   0x00

AUXDAC_VREF_SEL_ADCREF

#define AUXDAC_VREF_SEL_ADCREF   ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF

Referenced by AUXDACCalcMax(), AUXDACCalcMin(), and AUXDACSetVref().

AUXDAC_VREF_SEL_DCOUPL

#define AUXDAC_VREF_SEL_DCOUPL   ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL

Referenced by AUXDACCalcMax(), and AUXDACCalcMin().

AUXDAC_VREF_SEL_NC

#define AUXDAC_VREF_SEL_NC   ADI_4_AUX_MUX2_DAC_VREF_SEL_NC

Referenced by AUXDACCalcMax(), and AUXDACCalcMin().

AUXDAC_VREF_SEL_VDDS

#define AUXDAC_VREF_SEL_VDDS   ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS

Referenced by AUXDACCalcMax(), and AUXDACCalcMin().