SPICC26X4DMA Hardware attributes. More...
#include <SPICC26X4DMA.h>
Data Fields | |
uint32_t | baseAddr |
SPI Peripheral's base address. More... | |
uint8_t | intNum |
uint8_t | intPriority |
SPI CC26X4DMA Peripheral's interrupt priority. More... | |
uint32_t | swiPriority |
SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. More... | |
PowerCC26XX_Resource | powerMngrId |
uint16_t | defaultTxBufValue |
uint32_t | rxChannelBitMask |
uint32_t | txChannelBitMask |
volatile tDMAControlTable * | dmaTxTableEntryPri |
volatile tDMAControlTable * | dmaRxTableEntryPri |
volatile tDMAControlTable * | dmaTxTableEntryAlt |
volatile tDMAControlTable * | dmaRxTableEntryAlt |
int32_t | txPinMux |
int32_t | rxPinMux |
int32_t | clkPinMux |
int32_t | csnPinMux |
uint_least8_t | picoPin |
uint_least8_t | pociPin |
uint_least8_t | clkPin |
uint_least8_t | csnPin |
uint32_t | minDmaTransferSize |
SPICC26X4DMA Hardware attributes.
These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For CC26x4Ware these definitions are found in:
intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().
A sample structure is shown below:
uint32_t SPICC26X4DMA_HWAttrs::baseAddr |
SPI Peripheral's base address.
uint8_t SPICC26X4DMA_HWAttrs::intNum |
SPI CC26X4DMA Peripheral's interrupt vector
uint8_t SPICC26X4DMA_HWAttrs::intPriority |
SPI CC26X4DMA Peripheral's interrupt priority.
The CC26x4 uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).
(7 << 5) will apply the lowest priority.
(1 << 5) will apply the highest priority.
Setting the priority to 0 is not supported by this driver.
HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.
uint32_t SPICC26X4DMA_HWAttrs::swiPriority |
SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file.
PowerCC26XX_Resource SPICC26X4DMA_HWAttrs::powerMngrId |
SPI Peripheral's power manager ID
uint16_t SPICC26X4DMA_HWAttrs::defaultTxBufValue |
Default TX value if txBuf == NULL
uint32_t SPICC26X4DMA_HWAttrs::rxChannelBitMask |
uDMA controlTable channel index
uint32_t SPICC26X4DMA_HWAttrs::txChannelBitMask |
uDMA controlTable channel index
volatile tDMAControlTable* SPICC26X4DMA_HWAttrs::dmaTxTableEntryPri |
uDMA controlTable primary tx entry
volatile tDMAControlTable* SPICC26X4DMA_HWAttrs::dmaRxTableEntryPri |
uDMA controlTable primary tx entry
volatile tDMAControlTable* SPICC26X4DMA_HWAttrs::dmaTxTableEntryAlt |
uDMA controlTable alternate tx entry
volatile tDMAControlTable* SPICC26X4DMA_HWAttrs::dmaRxTableEntryAlt |
uDMA controlTable alternate rx entry
int32_t SPICC26X4DMA_HWAttrs::txPinMux |
Tx PIN mux value. Can be applied to either PICO or POCI
int32_t SPICC26X4DMA_HWAttrs::rxPinMux |
Rx PIN mux value. Can be applied to either PICO or POCI
int32_t SPICC26X4DMA_HWAttrs::clkPinMux |
CLK PIN mux value for flow control
int32_t SPICC26X4DMA_HWAttrs::csnPinMux |
CSN PIN mux value for flow control
uint_least8_t SPICC26X4DMA_HWAttrs::picoPin |
SPI PICO pin
uint_least8_t SPICC26X4DMA_HWAttrs::pociPin |
SPI POCI pin
uint_least8_t SPICC26X4DMA_HWAttrs::clkPin |
SPI CLK pin
uint_least8_t SPICC26X4DMA_HWAttrs::csnPin |
SPI CSN pin
uint32_t SPICC26X4DMA_HWAttrs::minDmaTransferSize |
Minimum transfer size for DMA based transfer