CC26xx Driver Library
[setup_rom.h] Setup (ROM functions)

Functions

void SetupAfterColdResetWakeupFromShutDownCfg1 (uint32_t ccfg_ModeConfReg)
 First part of configuration required after cold reset and when waking up from shutdown. More...
 
void SetupAfterColdResetWakeupFromShutDownCfg2 (uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)
 Second part of configuration required after cold reset and when waking up from shutdown. More...
 
void SetupAfterColdResetWakeupFromShutDownCfg3 (uint32_t ccfg_ModeConfReg)
 Third part of configuration required after cold reset and when waking up from shutdown. More...
 
uint32_t SetupGetTrimForAdcShModeEn (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. More...
 
uint32_t SetupGetTrimForAdcShVbufEn (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. More...
 
uint32_t SetupGetTrimForAmpcompCtrl (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAmpcompTh1 (void)
 Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAmpcompTh2 (void)
 Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForAnabypassValue1 (uint32_t ccfg_ModeConfReg)
 Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForDblrLoopFilterResetVoltage (uint32_t ui32Fcfg1Revision)
 Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. More...
 
uint32_t SetupGetTrimForRadcExtCfg (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. More...
 
uint32_t SetupGetTrimForRcOscLfIBiasTrim (uint32_t ui32Fcfg1Revision)
 Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. More...
 
uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim (void)
 Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscHfCtl (uint32_t ui32Fcfg1Revision)
 Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscHfFastStart (void)
 Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. More...
 
uint32_t SetupGetTrimForXoscHfIbiastherm (void)
 Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 register in OSC_DIG. More...
 
uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio (uint32_t ui32Fcfg1Revision)
 Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the returned value. More...
 
static int32_t SetupSignExtendVddrTrimValue (uint32_t ui32VddrTrimVal)
 Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) More...
 
void SetupSetCacheModeAccordingToCcfgSetting (void)
 Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) More...
 
void SetupSetAonRtcSubSecInc (uint32_t subSecInc)
 Doing the tricky stuff needed to enter new RTCSUBSECINC value. More...
 
void SetupStepVddrTrimTo (uint32_t toCode)
 Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max) More...
 

Detailed Description

This module contains functions from the Setup API which are likely to be in ROM.

Note
Do not use functions from this module directly! This module is only to be used by SetupTrimDevice().

Function Documentation

§ SetupAfterColdResetWakeupFromShutDownCfg1()

void SetupAfterColdResetWakeupFromShutDownCfg1 ( uint32_t  ccfg_ModeConfReg)

First part of configuration required after cold reset and when waking up from shutdown.

Configures the following based on settings in CCFG (Customer Configuration area:

  • Boost mode for CC13xx devices
  • Minimal VDDR voltage threshold used during sleep mode
  • DCDC functionality:
    • Selects if DCDC or GLDO regulator will be used for VDDR in active mode
    • Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode

In addition the battery monitor low limit for internal regulator mode is set to a hard coded value.

Parameters
ccfg_ModeConfRegis the value of the CCFG_O_MODE_CONF_1 register
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

167 {
168  // Check for CC1352 boost mode
169  // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
170  if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
171  (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
172  {
173  // Set VDDS_BOD trim - using masked write {MASK8:DATA8}
174  // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1
175  // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to
176  // latch new VDDS BOD. Set to 0 first to guarantee a positive transition.
177  HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
178  //
179  // VDDS_BOD_LEVEL = 1 means that boost mode is selected
180  // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31)
181  HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
182  ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
183  ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ;
184  HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
185 
186  SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
187  FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
188  FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
189  }
190 
191  // 1.
192  // Do not allow DCDC to be enabled if in external regulator mode.
193  // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg).
194  //
195  // 2.
196  // Adjusted battery monitor low limit in internal regulator mode.
197  // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
198  if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) {
199  ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M );
200  } else {
201  HWREG( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0 ) &= ~( AON_BATMON_FLASHPUMPP0_LOWLIM );
202  }
203 
204  // Enable or disable DCDC depending on CCFG:MODE_CONF:DCDC_ACTIVE
205  // Note 1: Inverse polarity -> if ( CCFG_.._ACTIVE = 1 ) then disable DCDC else enable DCDC
206  // Note 2: Both bits must be set equal (either both true or both false) - therefore testing only on the ACTIVE bit in CCFG.
207  if ( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) {
208  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) &= ~( AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE );
209  } else {
210  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) |= ( AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE );
211  }
212 }
void SetupStepVddrTrimTo(uint32_t toCode)
Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max) ...
Definition: setup_rom.c:118
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§ SetupAfterColdResetWakeupFromShutDownCfg2()

void SetupAfterColdResetWakeupFromShutDownCfg2 ( uint32_t  ui32Fcfg1Revision,
uint32_t  ccfg_ModeConfReg 
)

Second part of configuration required after cold reset and when waking up from shutdown.

Configures and trims functionalites required for use of XOSC_HF. The configurations and trimmings are based on settings in FCFG1 (Factory Configuration area) and partly on ccfg_ModeConfReg.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
ccfg_ModeConfRegis the value of the CCFG_O_MODE_CONF_1 register
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

221 {
222  uint32_t ui32Trim;
223 
224  // Following sequence is required for using XOSCHF, if not included
225  // devices crashes when trying to switch to XOSCHF.
226  //
227  // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
228  // register
229  ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg );
230  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
231 
232  // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
233  // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
235  DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
236  (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
237  DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
238  DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
239  ui32Trim);
240 
241  // Trim XOSCHF IBIAS THERM. Get and set trim value for the
242  // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
243  // register bit fields are set to 0.
244  ui32Trim = SetupGetTrimForXoscHfIbiastherm();
245  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
246  ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
247 
248  // Trim AMPCOMP settings required before switch to XOSCHF
249  ui32Trim = SetupGetTrimForAmpcompTh2();
250  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
251  ui32Trim = SetupGetTrimForAmpcompTh1();
252  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
253 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
254  ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
255 #else
256  ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
257 #endif
258  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
259 
260  // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance to FCFG1 setting
261  // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
262  // Using MASK4 write + 1 => writing to bits[7:4]
263  ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision );
264  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
265  ( 0x20 | ( ui32Trim << 1 ));
266 
267  // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting
268  // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
269  // Using MASK4 write + 1 => writing to bits[7:4]
270  ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision );
271  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
272  ( 0x10 | ( ui32Trim ));
273 
274  // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
275  // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
276  // Remaining register bit fields are set to their reset values of 0.
277  ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision);
278  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
279 
280  // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
281  // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
282  // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
283  // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
284  // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
285  ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
286  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
287  ( 0x60 | ( ui32Trim << 1 ));
288 
289  // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
290  // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
291  // This is DDI_0_OSC_O_ATESTCTL bit[7]
292  // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
293  // Using MASK4 write + 1 => writing to bits[7:4]
294  ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
295  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
296  ( 0x80 | ( ui32Trim << 3 ));
297 
298  // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
299  // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
300  // This can be simplified since the registers are packed together in the same
301  // order both in FCFG1 and in the HW register.
302  // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
303  // Using MASK8 write + 4 => writing to bits[23:16]
304  ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
305  HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
306  ( 0xFC00 | ( ui32Trim << 2 ));
307 
308  // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
309  // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
310  // Remaining register bit fields are set to their reset values of 0.
311  ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision);
312  DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
313 }
uint32_t SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.
Definition: setup_rom.c:722
uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision)
Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the retur...
Definition: setup_rom.c:861
void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)
Write a bit field via the DDI using 16-bit maskable write.
Definition: ddi.c:115
uint32_t SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.
Definition: setup_rom.c:741
uint32_t SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.
Definition: setup_rom.c:760
uint32_t SetupGetTrimForXoscHfIbiastherm(void)
Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 regist...
Definition: setup_rom.c:531
uint32_t SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.
Definition: setup_rom.c:810
uint32_t SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg)
Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.
Definition: setup_rom.c:435
uint32_t SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision)
Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.
Definition: setup_rom.c:842
uint32_t SetupGetTrimForAmpcompTh1(void)
Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.
Definition: setup_rom.c:586
uint32_t SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.
Definition: setup_rom.c:621
void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
Write a 32 bit value to a register in the DDI slave.
Definition: ddi.c:64
uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim(void)
Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in...
Definition: setup_rom.c:504
uint32_t SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.
Definition: setup_rom.c:703
uint32_t SetupGetTrimForAmpcompTh2(void)
Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.
Definition: setup_rom.c:551
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§ SetupAfterColdResetWakeupFromShutDownCfg3()

void SetupAfterColdResetWakeupFromShutDownCfg3 ( uint32_t  ccfg_ModeConfReg)

Third part of configuration required after cold reset and when waking up from shutdown.

Configures the following:

  • XOSC source selection based on ccfg_ModeConfReg. If HPOSC is selected on a HPOSC device the oscillator is configured based on settings in FCFG1 (Factory Configuration area).
  • Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver.
  • Duration of the XOSC_HF fast startup mode based on FCFG1 setting.
  • SCLK_LF based on ccfg_ModeConfReg.
  • Output voltage of ADC fixed reference based on FCFG1 setting.
Parameters
ccfg_ModeConfRegis the value of the CCFG_O_MODE_CONF_1 register
Returns
None

Referenced by TrimAfterColdResetWakeupFromShutDown().

322 {
323  uint32_t fcfg1OscConf;
324  uint32_t ui32Trim;
325  uint32_t currentHfClock;
326  uint32_t ccfgExtLfClk;
327 
328  // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC
329  switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) {
330  case 2 :
331  // XOSC source is a 48 MHz crystal
332  // Do nothing (since this is the reset setting)
333  break;
334  case 1 :
335  // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC)
336 
337  fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF );
338 
339  if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) {
340  // This is a HPOSC chip, apply HPOSC settings
341  // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0)
342  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN;
343 
344  // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit)
345  // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits)
346  // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits)
347  // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit)
348  // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits)
349  // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits)
350  // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit)
351 
352  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) &
353  ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) |
354  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) |
355  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) );
356  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) |
357  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) );
358  HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) &
359  ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) |
360  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) |
361  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) |
362  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) |
363  ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) );
364  break;
365  }
366  // Not a HPOSC chip - fall through to default
367  default :
368  // XOSC source is a 24 MHz crystal (default)
369  // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
370  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M;
371  break;
372  }
373 
374  // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO
375  // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used.
376  if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) {
377  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS;
378  }
379 
380  // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0.
381  // This is typically already 0 except on Lizard where it is set in ROM-boot
382  HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;
383 
384  // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
385  ui32Trim = SetupGetTrimForXoscHfFastStart();
386  HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim );
387 
388  // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
389  switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) {
390  case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz)
392  SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency
393  break;
394  case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT)
395  // Set SCLK_LF to use the same source as SCLK_HF
396  // Can be simplified a bit since possible return values for HF matches LF settings
397  currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF );
398  OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock );
399  while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) {
400  // Wait until switched
401  }
402  ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK );
403  SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S );
404  IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S,
406  IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis
407  // Set XOSC_LF in bypass mode to allow external 32 kHz clock
408  HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS;
409  // Fall through to set XOSC_LF as SCLK_LF source
410  case 2 : // XOSC_LF -> SLCK_LF (32768 Hz)
412  break;
413  default : // (=3) RCOSC_LF
415  break;
416  }
417 
418  // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
419  HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
420  ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
421  FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
422  ADI_4_AUX_ADCREF1_VTRIM_S ) &
423  ADI_4_AUX_ADCREF1_VTRIM_M );
424 
425  // Sync with AON
426  SysCtrlAonSync();
427 }
static void SysCtrlAonSync(void)
Sync all accesses to the AON register interface.
Definition: sys_ctrl.h:336
#define IOC_PORT_AON_CLK32K
Definition: ioc.h:184
uint32_t OSCClockSourceGet(uint32_t ui32SrcClk)
Get the source clock settings.
Definition: osc.c:150
#define IOC_STD_INPUT
Definition: ioc.h:349
#define OSC_SRC_CLK_HF
Definition: osc.h:118
#define OSC_XOSC_HF
Definition: osc.h:122
#define OSC_SRC_CLK_LF
Definition: osc.h:119
void SetupSetAonRtcSubSecInc(uint32_t subSecInc)
Doing the tricky stuff needed to enter new RTCSUBSECINC value.
Definition: setup_rom.c:926
#define OSC_RCOSC_LF
Definition: osc.h:123
void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)
Set the configuration of an IO port.
Definition: ioc.c:96
#define IOC_HYST_ENABLE
Definition: ioc.h:257
void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
Configure the oscillator input to the a source clock.
Definition: osc.c:113
uint32_t SetupGetTrimForXoscHfFastStart(void)
Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.
Definition: setup_rom.c:792
#define OSC_XOSC_LF
Definition: osc.h:124
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§ SetupGetTrimForAdcShModeEn()

uint32_t SetupGetTrimForAdcShModeEn ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

723 {
724  uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting
725 
726  if ( ui32Fcfg1Revision >= 0x00000022 ) {
727  getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
728  FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
729  FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
730  }
731 
732  return ( getTrimForAdcShModeEnValue );
733 }

§ SetupGetTrimForAdcShVbufEn()

uint32_t SetupGetTrimForAdcShVbufEn ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

742 {
743  uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting
744 
745  if ( ui32Fcfg1Revision >= 0x00000022 ) {
746  getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
747  FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
748  FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
749  }
750 
751  return ( getTrimForAdcShVbufEnValue );
752 }

§ SetupGetTrimForAmpcompCtrl()

uint32_t SetupGetTrimForAmpcompCtrl ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

622 {
623  uint32_t ui32TrimValue ;
624  uint32_t ui32Fcfg1Value ;
625  uint32_t ibiasOffset ;
626  uint32_t ibiasInit ;
627  uint32_t modeConf1 ;
628  int32_t deltaAdjust ;
629 
630  // Use device specific trim values located in factory configuration
631  // area. Register bit fields without trim values in the factory
632  // configuration area will be set to the value of 0.
633  ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
634 
635  ibiasOffset = ( ui32Fcfg1Value &
636  FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
637  FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
638  ibiasInit = ( ui32Fcfg1Value &
639  FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
640  FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
641 
642  if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
643  // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
644  modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
645 
646  // Both fields are signed 4-bit values. This is an assumption when doing the sign extension.
647  deltaAdjust =
648  (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )))
649  >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W ));
650  deltaAdjust += (int32_t)ibiasOffset;
651  if ( deltaAdjust < 0 ) {
652  deltaAdjust = 0;
653  }
654  if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
655  deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
656  }
657  ibiasOffset = (uint32_t)deltaAdjust;
658 
659  deltaAdjust =
660  (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )))
661  >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W ));
662  deltaAdjust += (int32_t)ibiasInit;
663  if ( deltaAdjust < 0 ) {
664  deltaAdjust = 0;
665  }
666  if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
667  deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
668  }
669  ibiasInit = (uint32_t)deltaAdjust;
670  }
671  ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
672  ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
673 
674  ui32TrimValue |= (((ui32Fcfg1Value &
675  FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
676  FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
677  DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
678  ui32TrimValue |= (((ui32Fcfg1Value &
679  FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
680  FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
681  DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
682  ui32TrimValue |= (((ui32Fcfg1Value &
683  FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
684  FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
685  DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
686 
687  if ( ui32Fcfg1Revision >= 0x00000022 ) {
688  ui32TrimValue |= ((( ui32Fcfg1Value &
689  FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
690  FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
691  DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
692  }
693 
694  return(ui32TrimValue);
695 }

§ SetupGetTrimForAmpcompTh1()

uint32_t SetupGetTrimForAmpcompTh1 ( void  )

Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

587 {
588  uint32_t ui32TrimValue;
589  uint32_t ui32Fcfg1Value;
590 
591  // Use device specific trim values located in factory configuration
592  // area. All defined register bit fields have a corresponding trim
593  // value in the factory configuration area
594  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
595  ui32TrimValue = (((ui32Fcfg1Value &
596  FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
597  FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
598  DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
599  ui32TrimValue |= (((ui32Fcfg1Value &
600  FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
601  FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
602  DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
603  ui32TrimValue |= (((ui32Fcfg1Value &
604  FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
605  FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
606  DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
607  ui32TrimValue |= (((ui32Fcfg1Value &
608  FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
609  FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
610  DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
611 
612  return(ui32TrimValue);
613 }

§ SetupGetTrimForAmpcompTh2()

uint32_t SetupGetTrimForAmpcompTh2 ( void  )

Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

552 {
553  uint32_t ui32TrimValue;
554  uint32_t ui32Fcfg1Value;
555 
556  // Use device specific trim value located in factory configuration
557  // area. All defined register bit fields have corresponding trim
558  // value in the factory configuration area
559  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
560  ui32TrimValue = ((ui32Fcfg1Value &
561  FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
562  FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
563  DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
564  ui32TrimValue |= (((ui32Fcfg1Value &
565  FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
566  FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
567  DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
568  ui32TrimValue |= (((ui32Fcfg1Value &
569  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
570  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
571  DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
572  ui32TrimValue |= (((ui32Fcfg1Value &
573  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
574  FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
575  DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
576 
577  return(ui32TrimValue);
578 }

§ SetupGetTrimForAnabypassValue1()

uint32_t SetupGetTrimForAnabypassValue1 ( uint32_t  ccfg_ModeConfReg)

Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.

Parameters
ccfg_ModeConfRegis the value of the CCFG_O_MODE_CONF_1 register
Returns
Returns the trim value.

Referenced by OSC_AdjustXoscHfCapArray(), and SetupAfterColdResetWakeupFromShutDownCfg2().

436 {
437  uint32_t ui32Fcfg1Value ;
438  uint32_t ui32XoscHfRow ;
439  uint32_t ui32XoscHfCol ;
440  uint32_t ui32TrimValue ;
441 
442  // Use device specific trim values located in factory configuration
443  // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
444  // the ANABYPASS_VALUE1 register. Value for the other bit fields
445  // are set to 0.
446 
447  ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
448  ui32XoscHfRow = (( ui32Fcfg1Value &
449  FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
450  FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
451  ui32XoscHfCol = (( ui32Fcfg1Value &
452  FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
453  FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
454 
455  if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
456  // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
457  // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
458  // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
459  // a define and sign extension must therefore be hard coded.
460  // ( A small test program is created verifying the code lines below:
461  // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
462  int32_t i32CustomerDeltaAdjust =
463  (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )))
464  >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W ));
465 
466  while ( i32CustomerDeltaAdjust < 0 ) {
467  ui32XoscHfCol >>= 1; // COL 1 step down
468  if ( ui32XoscHfCol == 0 ) { // if COL below minimum
469  ui32XoscHfCol = 0xFFFF; // Set COL to maximum
470  ui32XoscHfRow >>= 1; // ROW 1 step down
471  if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
472  ui32XoscHfRow = 1; // Set both ROW and COL
473  ui32XoscHfCol = 1; // to minimum
474  }
475  }
476  i32CustomerDeltaAdjust++;
477  }
478  while ( i32CustomerDeltaAdjust > 0 ) {
479  ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
480  if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum
481  ui32XoscHfCol = 1; // Set COL to minimum
482  ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
483  if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum
484  ui32XoscHfRow = 0xF; // Set both ROW and COL
485  ui32XoscHfCol = 0xFFFF; // to maximum
486  }
487  }
488  i32CustomerDeltaAdjust--;
489  }
490  }
491 
492  ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
493  ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
494 
495  return (ui32TrimValue);
496 }

§ SetupGetTrimForDblrLoopFilterResetVoltage()

uint32_t SetupGetTrimForDblrLoopFilterResetVoltage ( uint32_t  ui32Fcfg1Revision)

Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

704 {
705  uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
706 
707  if ( ui32Fcfg1Revision >= 0x00000020 ) {
708  dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
709  FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
710  FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
711  }
712 
713  return ( dblrLoopFilterResetVoltageValue );
714 }

§ SetupGetTrimForRadcExtCfg()

uint32_t SetupGetTrimForRadcExtCfg ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

811 {
812  uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting
813  uint32_t fcfg1Data;
814 
815  if ( ui32Fcfg1Revision >= 0x00000020 ) {
816  fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
817  getTrimForRadcExtCfgValue =
818  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
819  FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
820  DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
821 
822  getTrimForRadcExtCfgValue |=
823  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
824  FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
825  DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
826 
827  getTrimForRadcExtCfgValue |=
828  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
829  FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
830  DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
831  }
832 
833  return ( getTrimForRadcExtCfgValue );
834 }

§ SetupGetTrimForRcOscLfIBiasTrim()

uint32_t SetupGetTrimForRcOscLfIBiasTrim ( uint32_t  ui32Fcfg1Revision)

Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value from FCFG1.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

843 {
844  uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
845 
846  if ( ui32Fcfg1Revision >= 0x00000022 ) {
847  trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
848  FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
849  FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
850  }
851 
852  return ( trimForRcOscLfIBiasTrimValue );
853 }

§ SetupGetTrimForRcOscLfRtuneCtuneTrim()

uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim ( void  )

Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

505 {
506  uint32_t ui32TrimValue;
507 
508  // Use device specific trim values located in factory configuration
509  // area
510  ui32TrimValue =
511  ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
512  FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
513  FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
514  DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
515 
516  ui32TrimValue |=
517  ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
518  FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
519  FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
520  DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
521 
522  return(ui32TrimValue);
523 }

§ SetupGetTrimForXoscHfCtl()

uint32_t SetupGetTrimForXoscHfCtl ( uint32_t  ui32Fcfg1Revision)

Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

761 {
762  uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting
763  uint32_t fcfg1Data;
764 
765  if ( ui32Fcfg1Revision >= 0x00000020 ) {
766  fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
767  getTrimForXoschfCtlValue =
768  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
769  FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
770  DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
771 
772  getTrimForXoschfCtlValue |=
773  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
774  FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
775  DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
776 
777  getTrimForXoschfCtlValue |=
778  ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
779  FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
780  DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
781  }
782 
783  return ( getTrimForXoschfCtlValue );
784 }

§ SetupGetTrimForXoscHfFastStart()

uint32_t SetupGetTrimForXoscHfFastStart ( void  )

Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg3().

793 {
794  uint32_t ui32XoscHfFastStartValue ;
795 
796  // Get value from FCFG1
797  ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
798  FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
799  FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
800 
801  return ( ui32XoscHfFastStartValue );
802 }

§ SetupGetTrimForXoscHfIbiastherm()

uint32_t SetupGetTrimForXoscHfIbiastherm ( void  )

Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 register in OSC_DIG.

Returns
Returns the trim value.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

532 {
533  uint32_t ui32TrimValue;
534 
535  // Use device specific trim value located in factory configuration
536  // area
537  ui32TrimValue =
538  (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
539  FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
540  FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
541 
542  return(ui32TrimValue);
543 }

§ SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio()

uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ( uint32_t  ui32Fcfg1Revision)

Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the returned value.

Parameters
ui32Fcfg1Revisionis the value of the FCFG1_O_FCFG1_REVISION register
Returns
Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet.

Referenced by SetupAfterColdResetWakeupFromShutDownCfg2().

862 {
863  uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
864 
865  if ( ui32Fcfg1Revision >= 0x00000022 ) {
866  trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
867  ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
868  FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
869  FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
870  }
871 
872  return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
873 }

§ SetupSetAonRtcSubSecInc()

void SetupSetAonRtcSubSecInc ( uint32_t  subSecInc)

Doing the tricky stuff needed to enter new RTCSUBSECINC value.

Parameters
subSecInc
Returns
None

Referenced by OSC_HPOSCRtcCompensate(), SetupAfterColdResetWakeupFromShutDownCfg3(), SetupSignExtendVddrTrimValue(), and SetupTrimDevice().

927 {
928  // Loading a new RTCSUBSECINC value is done in 5 steps:
929  // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0
930  // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1
931  // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
932  // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK
933  // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
934  HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M );
935  HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M );
936 
937  HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ;
938  while( ! ( HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) & AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK ));
939  HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0;
940 
941 }

§ SetupSetCacheModeAccordingToCcfgSetting()

void SetupSetCacheModeAccordingToCcfgSetting ( void  )

Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)

Returns
None

Referenced by SetupSignExtendVddrTrimValue(), and SetupTrimDevice().

882 {
883  // - Make sure to enable aggressive VIMS clock gating for power optimization
884  // Only for PG2 devices.
885  // - Enable cache prefetch enable as default setting
886  // (Slightly higher power consumption, but higher CPU performance)
887  // - IF ( CCFG_..._DIS_GPRAM == 1 )
888  // then: Enable cache (set cache mode = 1), even if set by ROM boot code
889  // (This is done because it's not set by boot code when running inside
890  // a debugger supporting the Halt In Boot (HIB) functionality).
891  // else: Set MODE_GPRAM if not already set (see inline comments as well)
892  uint32_t vimsCtlMode0 ;
893 
894  while ( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_CHANGING ) {
895  // Do nothing - wait for an eventual ongoing mode change to complete.
896  // (There should typically be no wait time here, but need to be sure)
897  }
898 
899  // Note that Mode=0 is equal to MODE_GPRAM
900  vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M );
901 
902 
903  if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) {
904  // Enable cache (and hence disable GPRAM)
905  HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE );
906  } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) {
907  // GPRAM is enabled in CCFG but not selected
908  // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM
909  HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF );
910  while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) {
911  // Do nothing - wait for an eventual mode change to complete (This goes fast).
912  }
913  HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
914  } else {
915  // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set
916  HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
917  }
918 }

§ SetupSignExtendVddrTrimValue()

static int32_t SetupSignExtendVddrTrimValue ( uint32_t  ui32VddrTrimVal)
inlinestatic

Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)

Parameters
ui32VddrTrimVal
Returns
Returns Sign extended VDDR_TRIM setting.

Referenced by SetupStepVddrTrimTo().

316 {
317  // The VDDR trim value is 5 bits representing the range from -10 to +21
318  // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15)
319  int32_t i32SignedVddrVal = ui32VddrTrimVal;
320  if ( i32SignedVddrVal > 0x15 ) {
321  i32SignedVddrVal -= 0x20;
322  }
323  return ( i32SignedVddrVal );
324 }
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§ SetupStepVddrTrimTo()

void SetupStepVddrTrimTo ( uint32_t  toCode)

Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and setting VDDS_BOD to max)

Parameters
toCodespecifies the target VDDR trim value. The input parameter toCode can be either the signed extended trim value or holding the trim code bits only.
Returns
None

Referenced by SetupAfterColdResetWakeupFromShutDownCfg1(), and SetupSignExtendVddrTrimValue().

119 {
120  uint32_t pmctlResetctl_reg ;
121  int32_t targetTrim ;
122  int32_t currentTrim ;
123 
124  targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ));
125  currentTrim = SetupSignExtendVddrTrimValue((
126  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
127  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
128  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ;
129 
130  if ( targetTrim != currentTrim ) {
131  pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
132  if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
133  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M );
134  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate
135  }
136 
137  while ( targetTrim != currentTrim ) {
138  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
139 
140  if ( targetTrim > currentTrim ) currentTrim++;
141  else currentTrim--;
142 
143  HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = (
144  ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) |
145  ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
146  ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) );
147  }
148 
149  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
150 
151  if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
152  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
153  HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
154  HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg;
155  HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate
156  }
157  }
158 }
static int32_t SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal)
Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
Definition: setup_rom.h:315
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