Instance: SPI2
Component: SPI
Base address: 0x40009000
Thor SPI with master and slave capabilities
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4000 9020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4000 9028 |
|
RO |
32 |
0x0000 0000 |
0x0000 0030 |
0x4000 9030 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x4000 9038 |
|
WO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4000 9040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4000 9048 |
|
RW |
32 |
0x0000 0001 |
0x0000 00E0 |
0x4000 90E0 |
|
RO |
32 |
0x1411 0010 |
0x0000 00FC |
0x4000 90FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4000 9100 |
|
RW |
32 |
0x0000 0004 |
0x0000 0104 |
0x4000 9104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4000 9108 |
|
RW |
32 |
0x0000 0012 |
0x0000 010C |
0x4000 910C |
|
RO |
32 |
0x0000 000F |
0x0000 0110 |
0x4000 9110 |
|
RW |
32 |
0x0000 0000 |
0x0000 0114 |
0x4000 9114 |
|
RW |
32 |
0x0000 0000 |
0x0000 0118 |
0x4000 9118 |
|
RO |
32 |
0x0000 0000 |
0x0000 0130 |
0x4000 9130 |
|
RW |
32 |
0x0000 0000 |
0x0000 0140 |
0x4000 9140 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4000 9020 | Instance | 0x4000 9020 |
Description | This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||
7:0 | STAT | Interrupt index status
|
RO | 0x00 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4000 9028 | Instance | 0x4000 9028 |
Description | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMA_DONE_TX | DMA Done 1 event for TX event mask.
|
0 | ||||||||||||
7 | DMA_DONE_RX | DMA Done 1 event for RX event mask.
|
0 | ||||||||||||
6 | IDLE | SPI Idle event mask.
|
0 | ||||||||||||
5 | TXEMPTY | Transmit FIFO Empty event mask.
|
0 | ||||||||||||
4 | TX | Transmit FIFO event mask.
|
0 | ||||||||||||
3 | RX | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
|
0 | ||||||||||||
2 | RTOUT | Enable SPI Receive Time-Out event mask.
|
0 | ||||||||||||
1 | PER | Parity error event mask.
|
0 | ||||||||||||
0 | RXFIFO_OVF | RXFIFO overflow event mask.
|
0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4000 9030 | Instance | 0x4000 9030 |
Description | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMA_DONE_TX | DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
|
0 | ||||||||||||
7 | DMA_DONE_RX | DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
|
0 | ||||||||||||
6 | IDLE | SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.
|
0 | ||||||||||||
5 | TXEMPTY | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
|
0 | ||||||||||||
4 | TX | Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
|
0 | ||||||||||||
3 | RX | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
|
0 | ||||||||||||
2 | RTOUT | SPI Receive Time-Out event.
|
0 | ||||||||||||
1 | PER | Parity error event: this bit is set if a Parity error has been detected
|
0 | ||||||||||||
0 | RXFIFO_OVF | RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
|
0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4000 9038 | Instance | 0x4000 9038 |
Description | Masked interrupt status. This is an AND of the IMASK and RIS registers. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMA_DONE_TX | Masked DMA Done 1 event for TX.
|
0 | ||||||||||||
7 | DMA_DONE_RX | Masked DMA Done 1 event for RX.
|
0 | ||||||||||||
6 | IDLE | Masked SPI IDLE mode event.
|
0 | ||||||||||||
5 | TXEMPTY | Masked Transmit FIFO Empty event.
|
0 | ||||||||||||
4 | TX | Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
|
0 | ||||||||||||
3 | RX | Masked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
|
0 | ||||||||||||
2 | RTOUT | Masked SPI Receive Time-Out Interrupt.
|
0 | ||||||||||||
1 | PER | Masked Parity error event: this bit if a Parity error has been detected
|
0 | ||||||||||||
0 | RXFIFO_OVF | Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
|
0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4000 9040 | Instance | 0x4000 9040 |
Description | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMA_DONE_TX | Set DMA Done 1 event for TX.
|
0 | ||||||||||||
7 | DMA_DONE_RX | Set DMA Done 1 event for RX.
|
0 | ||||||||||||
6 | IDLE | Set SPI IDLE mode event.
|
0 | ||||||||||||
5 | TXEMPTY | Set Transmit FIFO Empty event.
|
0 | ||||||||||||
4 | TX | Set Transmit FIFO event.
|
0 | ||||||||||||
3 | RX | Set Receive FIFO event.
|
0 | ||||||||||||
2 | RTOUT | Set SPI Receive Time-Out Event.
|
0 | ||||||||||||
1 | PER | Set Parity error event.
|
0 | ||||||||||||
0 | RXFIFO_OVF | Set RXFIFO overflow event.
|
0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4000 9048 | Instance | 0x4000 9048 |
Description | Interrupt clear. Write a 1 to clear corresponding Interrupt. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMA_DONE_TX | Clear DMA Done 1 event for TX.
|
0 | ||||||||||||
7 | DMA_DONE_RX | Clear DMA Done 1 event for RX.
|
0 | ||||||||||||
6 | IDLE | Clear SPI IDLE mode event.
|
0 | ||||||||||||
5 | TXEMPTY | Clear Transmit FIFO Empty event.
|
0 | ||||||||||||
4 | TX | Clear Transmit FIFO event.
|
0 | ||||||||||||
3 | RX | Clear Receive FIFO event.
|
0 | ||||||||||||
2 | RTOUT | Clear SPI Receive Time-Out Event.
|
0 | ||||||||||||
1 | PER | Clear Parity error event.
|
0 | ||||||||||||
0 | RXFIFO_OVF | Clear RXFIFO overflow event.
|
0 |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x4000 90E0 | Instance | 0x4000 90E0 |
Description | Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS) Note: The recommendation is to use SPI in the software mode |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
1:0 | INT0_CFG | Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0
|
RW | 0b01 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x4000 90FC | Instance | 0x4000 90FC |
Description | This register identifies the peripheral and its exact version. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:16 | MODULEID | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
|
0x1411 | ||||||||||||
15:12 | FEATUREVER | Feature Set for the module *instance*
|
0x0 | ||||||||||||
11:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | |||||||||||
7:4 | MAJREV | Major rev of the IP
|
0x1 | ||||||||||||
3:0 | MINREV | Minor rev of the IP
|
0x0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4000 9100 | Instance | 0x4000 9100 |
Description | SPI control register 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | CSCLR | Clear shift register counter on CS inactive This bit is relevant only in the slave mode, MS=0. 0: The shift counter will keep its state when CS goes low 1: The shift counter will be clear when CS goes low
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | SPH | CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0h = 1ST_CLK_EDGE : Data is captured on the first clock edge transition. 1h = 2ND_CLK_EDGE : Data is captured on the second clock edge transition.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | SPO | CLKOUT polarity (Motorola SPI frame format only) 0h = SPI produces a steady state LOW value on the CLKOUT pin when data is not being transferred. 1h = SPI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:5 | FRF | Frame format Select
|
RW | 0b00 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | DSS | Data Size Select. Note: Master mode: Values 0 - 2 are reserved and shall not be used. This will map to 4 bit mode. 3h = 4_BIT : 4-bit data Slave mode: DSS should be no less than 6 which means the minimum frame length is 7 bits.
|
RW | 0b0 0000 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4000 9104 | Instance | 0x4000 9104 |
Description | SPI control register 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||
29:24 | RXTIMEOUT | Receive Timeout (only for Slave mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Master mode configuration. A value of 0 disables this function.
|
RW | 0b00 0000 | ||||||||||||||
23:16 | REPEATTX | Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a slave.
|
RW | 0x00 | ||||||||||||||
15:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b0 0000 | ||||||||||||||
10 | FIFORST | This bit is used to reset transmit and receive FIFO pointers. The pointers are held at a reset value until bit is cleared to zero.
|
RW | 0 | ||||||||||||||
9:8 | MODE | SPI Communication Mode Select Note: Reserved/undefined Modes are identical to Legacy mode. MultiSPI mode is not supported
|
RW | 0b00 | ||||||||||||||
7 | PBS | Parity Bit Select: Disabled: Bit 0 is used for Parity Enabled: Bit 1 is used for Parity, Bit 0 is ignored
|
RW | 0 | ||||||||||||||
6 | PES | Even Parity Select
|
RW | 0 | ||||||||||||||
5 | PEN | Parity enable if enabled the last bit will be used as parity to evaluate the right transmission of the previous bits. In case of a parity miss-match the parity error flag RIS.PER will be set.
|
RW | 0 | ||||||||||||||
4 | MSB | MSB first select. Controls the direction of the receive and transmit shift register. 0b = LSB first 1b = MSB first
|
RW | 0 | ||||||||||||||
3 | SOD | Slave-mode: Data output disabled This bit is relevant only in the slave mode, MS=0. In multiple-slave systems, it is possible for an SPI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SPI slave is not supposed to drive the TXD line: 0: SPI can drive the MISO output in slave mode. 1: SPI cannot drive the MISO output in slave mode.
|
RW | 0 | ||||||||||||||
2 | MS | Master or slave mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0. 0h = Device configured as slave 1h = Device configured as master
|
RW | 1 | ||||||||||||||
1 | LBM | Loop back mode: 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally.
|
RW | 0 | ||||||||||||||
0 | ENABLE | SPI enable 0b = Disabled. SPI is disabled and logic held in reset state. 1b = Enabled. SPI released for operation.
|
RW | 0 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4000 9108 | Instance | 0x4000 9108 |
Description | Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:28 | DSAMPLE | Delayed sampling. In master mode the data on the input pin will be delayed sampled by the defined clock cycles. Note: As an example, if the SPI transmit frequency is set to 12 MHz in the master mode, DSAMPLE should be set to a value of 2
|
RW | 0x0 | |||||||||||
27:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||
9:0 | SCR | Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023.
|
RW | 0b00 0000 0000 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4000 910C | Instance | 0x4000 910C |
Description | The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
5:3 | RXIFLSEL | SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
|
RW | 0b010 | |||||||||||||||||||||||||||||
2:0 | TXIFLSEL | SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
|
RW | 0b010 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4000 9110 | Instance | 0x4000 9110 |
Description | Status Register | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
4 | BUSY | Busy
|
0 | ||||||||||||
3 | RNF | Receive FIFO not full
|
1 | ||||||||||||
2 | RFE | Receive FIFO empty.
|
1 | ||||||||||||
1 | TNF | Transmit FIFI not full
|
1 | ||||||||||||
0 | TFE | Transmit FIFO empty.
|
1 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4000 9114 | Instance | 0x4000 9114 |
Description | This register is used to specify module-specific divide ratio of the functional clock. (Only in Core Domain, for ULL use the CLKDIV in IPSTANDARD.) |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | RATIO | Selects divide ratio of module clock
|
RW | 0b000 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4000 9118 | Instance | 0x4000 9118 |
Description | DMA Control Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
1 | TXDMAE | Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. | RW | 0 | ||
0 | RXDMAE | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. | RW | 0 |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4000 9130 | Instance | 0x4000 9130 |
Description | RXDATA Register Reading this register returns first value in the FIFO. If the FIFO is empty the last read value is returned. Writing has not effect and is ignored. Core Domain SPI can use up to 32 bits ULL Domain SPI can use up to 16 bits |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:0 | DATA | Received Data Core Domain SPI: 32-bits wide data register ULL Domain SPI: 16-bits wide data register When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer.
|
RO | 0x0000 0000 |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x4000 9140 | Instance | 0x4000 9140 |
Description | TXDATA Register Writing put the data into the TX FIFO Reading this register returns the last written value. Core Domain SPI can use up to 32 bits ULL Domain SPI can use up to 16 bits |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:0 | DATA | Transmit Data 32-bits wide data register: When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer, is accessed. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 32 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.
|
RW | 0x0000 0000 |
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