SPI0

Instance: SPI0
Component: SPI
Base address: 0x40000000


Thor SPI with master and slave capabilities

TOP:SPI0 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IIDX

RO

32

0x0000 0000

0x0000 0020

0x4000 0020

IMASK

RW

32

0x0000 0000

0x0000 0028

0x4000 0028

RIS

RO

32

0x0000 0000

0x0000 0030

0x4000 0030

MIS

RO

32

0x0000 0000

0x0000 0038

0x4000 0038

ISET

WO

32

0x0000 0000

0x0000 0040

0x4000 0040

ICLR

WO

32

0x0000 0000

0x0000 0048

0x4000 0048

EVT_MODE

RW

32

0x0000 0001

0x0000 00E0

0x4000 00E0

DESC

RO

32

0x1411 0010

0x0000 00FC

0x4000 00FC

CTL0

RW

32

0x0000 0000

0x0000 0100

0x4000 0100

CTL1

RW

32

0x0000 0004

0x0000 0104

0x4000 0104

CLKCTL

RW

32

0x0000 0000

0x0000 0108

0x4000 0108

IFLS

RW

32

0x0000 0012

0x0000 010C

0x4000 010C

STAT

RO

32

0x0000 000F

0x0000 0110

0x4000 0110

CLKDIV2

RW

32

0x0000 0000

0x0000 0114

0x4000 0114

DMACR

RW

32

0x0000 0000

0x0000 0118

0x4000 0118

RXDATA

RO

32

0x0000 0000

0x0000 0130

0x4000 0130

TXDATA

RW

32

0x0000 0000

0x0000 0140

0x4000 0140

TOP:SPI0 Register Descriptions

TOP:SPI0:IIDX

Address Offset 0x0000 0020
Physical Address 0x4000 0020 Instance 0x4000 0020
Description This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 STAT Interrupt index status
Value ENUM Name Description
0x0 NO_INTR No interrupt pending
0x1 RXFIFO_OFV_EVT RX FIFO Overflow Event/interrupt pending
0x2 PER_EVT Transmit Parity Event/interrupt pending
0x3 RTOUT_EVT SPI receive time-out interrupt
0x4 RX_EVT Receive Event/interrupt pending
0x5 TX_EVT Transmit Event/interrupt pending
0x6 TX_EMPTY Transmit Buffer Empty Event/interrupt pending
0x7 IDLE_EVT End of Transmit Event/interrupt pending
0x8 DMA_DONE_RX_EVT DMA Done for Receive Event/interrupt pending
0x9 DMA_DONE_TX_EVT DMA Done for Transmit Event/interrupt pending
RO 0x00

TOP:SPI0:IMASK

Address Offset 0x0000 0028
Physical Address 0x4000 0028 Instance 0x4000 0028
Description Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_DONE_TX DMA Done 1 event for TX event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
7 DMA_DONE_RX DMA Done 1 event for RX event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
6 IDLE SPI Idle event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
5 TXEMPTY Transmit FIFO Empty event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
4 TX Transmit FIFO event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
3 RX Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
2 RTOUT Enable SPI Receive Time-Out event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
1 PER Parity error event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
0 RXFIFO_OVF RXFIFO overflow event mask.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0

TOP:SPI0:RIS

Address Offset 0x0000 0030
Physical Address 0x4000 0030 Instance 0x4000 0030
Description Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_DONE_TX DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
7 DMA_DONE_RX DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
6 IDLE SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
5 TXEMPTY Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
4 TX Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
3 RX Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
2 RTOUT SPI Receive Time-Out event.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
1 PER Parity error event: this bit is set if a Parity error has been detected
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
0 RXFIFO_OVF RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0

TOP:SPI0:MIS

Address Offset 0x0000 0038
Physical Address 0x4000 0038 Instance 0x4000 0038
Description Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_DONE_TX Masked DMA Done 1 event for TX.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
7 DMA_DONE_RX Masked DMA Done 1 event for RX.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
6 IDLE Masked SPI IDLE mode event.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
5 TXEMPTY Masked Transmit FIFO Empty event.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
4 TX Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
3 RX Masked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
2 RTOUT Masked SPI Receive Time-Out Interrupt.
Value ENUM Name Description
0x0 CLR Clear Interrupt Mask
0x1 SET Set Interrupt Mask
0
1 PER Masked Parity error event: this bit if a Parity error has been detected
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0
0 RXFIFO_OVF Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
Value ENUM Name Description
0x0 CLR Interrupt did not occur
0x1 SET Interrupt occurred
0

TOP:SPI0:ISET

Address Offset 0x0000 0040
Physical Address 0x4000 0040 Instance 0x4000 0040
Description Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_DONE_TX Set DMA Done 1 event for TX.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
7 DMA_DONE_RX Set DMA Done 1 event for RX.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
6 IDLE Set SPI IDLE mode event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
5 TXEMPTY Set Transmit FIFO Empty event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
4 TX Set Transmit FIFO event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
3 RX Set Receive FIFO event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
2 RTOUT Set SPI Receive Time-Out Event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt Mask
0
1 PER Set Parity error event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0
0 RXFIFO_OVF Set RXFIFO overflow event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 SET Set Interrupt
0

TOP:SPI0:ICLR

Address Offset 0x0000 0048
Physical Address 0x4000 0048 Instance 0x4000 0048
Description Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 DMA_DONE_TX Clear DMA Done 1 event for TX.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
7 DMA_DONE_RX Clear DMA Done 1 event for RX.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
6 IDLE Clear SPI IDLE mode event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
5 TXEMPTY Clear Transmit FIFO Empty event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
4 TX Clear Transmit FIFO event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
3 RX Clear Receive FIFO event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
2 RTOUT Clear SPI Receive Time-Out Event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Set Interrupt Mask
0
1 PER Clear Parity error event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0
0 RXFIFO_OVF Clear RXFIFO overflow event.
Value ENUM Name Description
0x0 NO_EFFECT Writing 0 has no effect
0x1 CLR Clear Interrupt
0

TOP:SPI0:EVT_MODE

Address Offset 0x0000 00E0
Physical Address 0x4000 00E0 Instance 0x4000 00E0
Description Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Note: The recommendation is to use SPI in the software mode
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 INT0_CFG Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0
Value ENUM Name Description
0x0 DISABLE The interrupt or event line is disabled.
0x1 SOFTWARE The interrupt or event line is in software mode. Software must clear the RIS.
0x2 HARDWARE The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
RW 0b01

TOP:SPI0:DESC

Address Offset 0x0000 00FC
Physical Address 0x4000 00FC Instance 0x4000 00FC
Description This register identifies the peripheral and its exact version.
Type RO
Bits Field Name Description Type Reset
31:16 MODULEID Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFF MAXIMUM Highest possible value
0x1411
15:12 FEATUREVER Feature Set for the module *instance*
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
0x0
11:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
7:4 MAJREV Major rev of the IP
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
0x1
3:0 MINREV Minor rev of the IP
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
0x0

TOP:SPI0:CTL0

Address Offset 0x0000 0100
Physical Address 0x4000 0100 Instance 0x4000 0100
Description SPI control register 0
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 CSCLR Clear shift register counter on CS inactive
This bit is relevant only in the slave mode, MS=0.
0: The shift counter will keep its state when CS goes low
1: The shift counter will be clear when CS goes low
Value ENUM Name Description
0x0 DISABLE Disable automatic clear of shift register when CS goes to disable.
0x1 ENABLE Enable automatic clear of shift register when CS goes to disable.
RW 0
13:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9 SPH CLKOUT phase (Motorola SPI frame format only)
This bit selects the clock edge that captures data and enables it to change state. It
has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
0h = 1ST_CLK_EDGE : Data is captured on the first clock edge transition.
1h = 2ND_CLK_EDGE : Data is captured on the second clock edge transition.
Value ENUM Name Description
0x0 FIRST Data is captured on the first clock edge transition.
0x1 SECOND Data is captured on the second clock edge transition.
RW 0
8 SPO CLKOUT polarity (Motorola SPI frame format only)
0h = SPI produces a steady state LOW value on the CLKOUT pin when data is not being transferred.
1h = SPI produces a steady state HIGH value on the CLKOUT pin when data is not being transferred.
Value ENUM Name Description
0x0 LOW SPI produces a steady state LOW value on the CLKOUT
0x1 HIGH SPI produces a steady state HIGH value on the CLKOUT
RW 0
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:5 FRF Frame format Select
Value ENUM Name Description
0x0 MOTOROLA_3WIRE Motorola SPI frame format (3 wire mode)
0x1 MOTOROLA_4WIRE Motorola SPI frame format (4 wire mode)
0x2 TI_SYNC TI synchronous serial frame format
0x3 MIRCOWIRE National Microwire frame format
RW 0b00
4:0 DSS Data Size Select.
Note:
Master mode: Values 0 - 2 are reserved and shall not be used. This will map to 4 bit mode. 3h = 4_BIT : 4-bit data
Slave mode: DSS should be no less than 6 which means the minimum frame length is 7 bits.
Value ENUM Name Description
0x3 DSS_4 Data Size Select bits: 4
0x4 DSS_5 Data Size Select bits: 5
0x5 DSS_6 Data Size Select bits: 6
0x6 DSS_7 Data Size Select bits: 7
0x7 DSS_8 Data Size Select bits: 8
0x8 DSS_9 Data Size Select bits: 9
0x9 DSS_10 Data Size Select bits: 10
0xA DSS_11 Data Size Select bits: 11
0xB DSS_12 Data Size Select bits: 12
0xC DSS_13 Data Size Select bits: 13
0xD DSS_14 Data Size Select bits: 14
0xE DSS_15 Data Size Select bits: 15
0xF DSS_16 Data Size Select bits: 16
0x10 DSS_17 Data Size Select bits: 17
0x11 DSS_18 Data Size Select bits: 18
0x12 DSS_19 Data Size Select bits: 19
0x13 DSS_20 Data Size Select bits: 20
0x14 DSS_21 Data Size Select bits: 21
0x15 DSS_22 Data Size Select bits: 22
0x16 DSS_23 Data Size Select bits: 23
0x17 DSS_24 Data Size Select bits: 24
0x18 DSS_25 Data Size Select bits: 25
0x19 DSS_26 Data Size Select bits: 26
0x1A DSS_27 Data Size Select bits: 27
0x1B DSS_28 Data Size Select bits: 28
0x1C DSS_29 Data Size Select bits: 29
0x1D DSS_30 Data Size Select bits: 30
0x1E DSS_31 Data Size Select bits: 31
0x1F DSS_32 Data Size Select bits: 32
RW 0b0 0000

TOP:SPI0:CTL1

Address Offset 0x0000 0104
Physical Address 0x4000 0104 Instance 0x4000 0104
Description SPI control register 1
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:24 RXTIMEOUT Receive Timeout (only for Slave mode)
Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set.
The time is calculated using the control register for the clock selection and divider in the Master mode configuration.
A value of 0 disables this function.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0x3F MAXIMUM Highest possible value
RW 0b00 0000
23:16 REPEATTX Counter to repeat last transfer
0: repeat last transfer is disabled.
x: repeat the last transfer with the given number.
The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total.
The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here.
It can be used to clean a transfer or to pull a certain amount of data by a slave.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFF MAXIMUM Highest possible value
RW 0x00
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000
10 FIFORST This bit is used to reset transmit and receive FIFO pointers. The pointers are held at a reset value until bit is cleared to zero.
Value ENUM Name Description
0x0 CLR Clear FIFO pointers reset trigger
0x1 SET Set FIFO pointers reset trigger
RW 0
9:8 MODE SPI Communication Mode Select
Note: Reserved/undefined Modes are identical to Legacy mode. MultiSPI mode is not supported
Value ENUM Name Description
0x0 LEGACY Legacy Mode
0x2 MULTISPI2 multiSPI Mode with 2 Data Bits (not supported)
0x3 MULTISPI4 multiSPI Mode with 4 Data Bits (not supported)
RW 0b00
7 PBS Parity Bit Select:
Disabled: Bit 0 is used for Parity
Enabled: Bit 1 is used for Parity, Bit 0 is ignored
Value ENUM Name Description
0x0 DISABLE Bit 0 is used for Parity
0x1 ENABLE Bit 1 is used for Parity, Bit 0 is ignored
RW 0
6 PES Even Parity Select
Value ENUM Name Description
0x0 DISABLE Odd Parity mode
0x1 ENABLE Even Parity mode
RW 0
5 PEN Parity enable
if enabled the last bit will be used as parity to evaluate the right transmission of the previous bits.
In case of a parity miss-match the parity error flag RIS.PER will be set.
Value ENUM Name Description
0x0 DISABLE Disable Parity function
0x1 ENABLE Enable Parity function
RW 0
4 MSB MSB first select. Controls the direction of the receive and transmit shift register.
0b = LSB first
1b = MSB first
Value ENUM Name Description
0x0 DISABLE LSB first
0x1 ENABLE MSB first
RW 0
3 SOD Slave-mode: Data output disabled
This bit is relevant only in the slave mode, MS=0. In multiple-slave systems, it is possible for an SPI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SPI slave is not supposed to drive the TXD line:
0: SPI can drive the MISO output in slave mode.
1: SPI cannot drive the MISO output in slave mode.
Value ENUM Name Description
0x0 DISABLE SPI can drive the MISO output in slave mode.
0x1 ENABLE SPI cannot drive the MISO output in slave mode.
RW 0
2 MS Master or slave mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.
0h = Device configured as slave
1h = Device configured as master
Value ENUM Name Description
0x0 DISABLE Select Slave Mode
0x1 ENABLE Select Master Mode
RW 1
1 LBM Loop back mode:
0: Normal serial port operation enabled.
1: Output of transmit serial shifter is connected to input of receive serial shifter internally.
Value ENUM Name Description
0x0 DISABLE Disable loopback mode
0x1 ENABLE Enable loopback mode
RW 0
0 ENABLE SPI enable
0b = Disabled. SPI is disabled and logic held in reset state.
1b = Enabled. SPI released for operation.
Value ENUM Name Description
0x0 DISABLE Disable module function
0x1 ENABLE Enable module function
RW 0

TOP:SPI0:CLKCTL

Address Offset 0x0000 0108
Physical Address 0x4000 0108 Instance 0x4000 0108
Description Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.
Type RW
Bits Field Name Description Type Reset
31:28 DSAMPLE Delayed sampling. In master mode the data on the input pin will be delayed sampled by the defined clock cycles.
Note: As an example, if the SPI transmit frequency is set to 12 MHz in the master mode, DSAMPLE should be set to a value of 2
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xF MAXIMUM Highest possible value
RW 0x0
27:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
9:0 SCR Serial clock divider:
This is used to generate the transmit and receive bit rate of the SPI.
The SPI bit rate is
(SPI's functional clock frequency)/((SCR+1)*2).
SCR is a value from 0-1023.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0x3FF MAXIMUM Highest possible value
RW 0b00 0000 0000

TOP:SPI0:IFLS

Address Offset 0x0000 010C
Physical Address 0x4000 010C Instance 0x4000 010C
Description The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:3 RXIFLSEL SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
Value ENUM Name Description
0x0 LVL_OFF Reserved
0x1 LVL_1_4 RX FIFO >= 1/4 full
0x2 LVL_1_2 RX FIFO >= 1/2 full (default)
0x3 LVL_3_4 RX FIFO >= 3/4 full
0x4 LVL_RES4 Reserved
0x5 LVL_FULL RX FIFO is full
0x6 LVL_RES6 Reserved
0x7 LEVEL_1 Trigger when RX FIFO contains >= 1 byte
Should be used with DMA
RW 0b010
2:0 TXIFLSEL SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
Value ENUM Name Description
0x0 LVL_OFF Reserved
0x1 LVL_3_4 TX FIFO <= 3/4 empty
0x2 LVL_1_2 TX FIFO <= 1/2 empty (default)
0x3 LVL_1_4 TX FIFO <= 1/4 empty
0x4 LVL_RES4 Reserved
0x5 LVL_EMPTY TX FIFO is empty
0x6 LVL_RES6 Reserved
0x7 LEVEL_1 Trigger when TX FIFO has >= 1 byte free
Should be used with DMA
RW 0b010

TOP:SPI0:STAT

Address Offset 0x0000 0110
Physical Address 0x4000 0110 Instance 0x4000 0110
Description Status Register
Type RO
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4 BUSY Busy
Value ENUM Name Description
0x0 IDLE SPI is in idle mode.
0x1 ACTIVE SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
0
3 RNF Receive FIFO not full
Value ENUM Name Description
0x0 FULL Receive FIFO is full.
0x1 NOT_FULL Receive FIFO is not full.
1
2 RFE Receive FIFO empty.
Value ENUM Name Description
0x0 NOT_EMPTY Receive FIFO is not empty.
0x1 EMPTY Receive FIFO is empty.
1
1 TNF Transmit FIFI not full
Value ENUM Name Description
0x0 FULL Transmit FIFO is full.
0x1 NOT_FULL Transmit FIFO is not full.
1
0 TFE Transmit FIFO empty.
Value ENUM Name Description
0x0 NOT_EMPTY Transmit FIFO is not empty.
0x1 EMPTY Transmit FIFO is empty.
1

TOP:SPI0:CLKDIV2

Address Offset 0x0000 0114
Physical Address 0x4000 0114 Instance 0x4000 0114
Description This register is used to specify module-specific divide ratio of the functional clock.
(Only in Core Domain, for ULL use the CLKDIV in IPSTANDARD.)
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 RATIO Selects divide ratio of module clock
Value ENUM Name Description
0x0 DIV_BY_1 Do not divide clock source
0x1 DIV_BY_2 Divide clock source by 2
0x2 DIV_BY_3 Divide clock source by 3
0x3 DIV_BY_4 Divide clock source by 4
0x4 DIV_BY_5 Divide clock source by 5
0x5 DIV_BY_6 Divide clock source by 6
0x6 DIV_BY_7 Divide clock source by 7
0x7 DIV_BY_8 Divide clock source by 8
RW 0b000

TOP:SPI0:DMACR

Address Offset 0x0000 0118
Physical Address 0x4000 0118 Instance 0x4000 0118
Description DMA Control Register
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1 TXDMAE Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. RW 0
0 RXDMAE Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RW 0

TOP:SPI0:RXDATA

Address Offset 0x0000 0130
Physical Address 0x4000 0130 Instance 0x4000 0130
Description RXDATA Register
Reading this register returns first value in the FIFO. If the FIFO is empty the last read value is returned.
Writing has not effect and is ignored.
Core Domain SPI can use up to 32 bits
ULL Domain SPI can use up to 16 bits
Type RO
Bits Field Name Description Type Reset
31:0 DATA Received Data
Core Domain SPI: 32-bits wide data register
ULL Domain SPI: 16-bits wide data register
When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer.
Received data less than 16 bits is automatically right justified in the receive buffer.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFF MAX16BIT Highest possible value
0xFFFFFFFF MAXIMUM Highest possible value
RO 0x0000 0000

TOP:SPI0:TXDATA

Address Offset 0x0000 0140
Physical Address 0x4000 0140 Instance 0x4000 0140
Description TXDATA Register
Writing put the data into the TX FIFO
Reading this register returns the last written value.
Core Domain SPI can use up to 32 bits
ULL Domain SPI can use up to 16 bits
Type RW
Bits Field Name Description Type Reset
31:0 DATA Transmit Data
32-bits wide data register:
When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer, is accessed.
When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate.
When a data size of less than 32 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.
Value ENUM Name Description
0x0 MINIMUM Smallest value
0xFFFF MAX16BIT Highest possible value
0xFFFFFFFF MAXIMUM Highest possible value
RW 0x0000 0000


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