Instance: CPU_SYSTICK
Component: CPU_SYSTICK
Base address: 0xE000E010
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 E010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 E014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 E018 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0xE000 E01C |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 E010 | Instance | 0xE000 E010 |
| Description | Controls the SysTick timer and provides status data `FTSSS | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
| 16 | COUNTFLAG | Indicates whether the counter has counted to zero since the last read of this register | RW | 0 | ||
| 15:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 | ||
| 2 | CLKSOURCE | Indicates the SysTick clock source | RW | 0 | ||
| 1 | TICKINT | Indicates whether counting to 0 causes the status of the SysTick exception to change to pending | RW | 0 | ||
| 0 | ENABLE | Indicates the enabled status of the SysTick counter | RW | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 E014 | Instance | 0xE000 E014 |
| Description | Provides access SysTick timer counter reload value `FTSSS | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | RELOAD | The value to load into the SYST_CVR `FTSSS when the counter reaches 0 | RW | 0x00 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 E018 | Instance | 0xE000 E018 |
| Description | Reads or clears the SysTick timer current counter value `FTSSS | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23:0 | CURRENT | Writing any value clears the SysTick timer counter `FTSSS to zero | WO | 0x00 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 E01C | Instance | 0xE000 E01C |
| Description | Reads the SysTick timer calibration value and parameters `FTSSS | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | NOREF | Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented | RO | 0 | ||
| 30 | SKEW | Indicates whether the 10ms calibration value is exact | RO | 0 | ||
| 29:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 23:0 | TENMS | Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If this field is zero, the calibration value is not known | RO | 0x00 0000 | ||
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