Instance: CPU_SIG
Component: CPU_SIG
Base address: 0xE000EF00
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 EF00 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 EF00 | Instance | 0xE000 EF00 |
| Description | Provides a mechanism for software to generate an interrupt | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8:0 | INTID | Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) | WO | 0b0 0000 0000 | ||
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