Instance: CPU_NVIC
Component: CPU_NVIC
Base address: 0xE000E100
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 E100 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 E104 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 E108 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0xE000 E180 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0xE000 E184 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0xE000 E188 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0xE000 E200 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0xE000 E204 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0xE000 E208 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0180 |
0xE000 E280 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0184 |
0xE000 E284 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0188 |
0xE000 E288 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0200 |
0xE000 E300 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0204 |
0xE000 E304 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0208 |
0xE000 E308 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0280 |
0xE000 E380 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0284 |
0xE000 E384 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0288 |
0xE000 E388 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0300 |
0xE000 E400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0304 |
0xE000 E404 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0308 |
0xE000 E408 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 030C |
0xE000 E40C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0310 |
0xE000 E410 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0314 |
0xE000 E414 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0318 |
0xE000 E418 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 031C |
0xE000 E41C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0320 |
0xE000 E420 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0324 |
0xE000 E424 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0328 |
0xE000 E428 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 032C |
0xE000 E42C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0330 |
0xE000 E430 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0334 |
0xE000 E434 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0338 |
0xE000 E438 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 033C |
0xE000 E43C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0340 |
0xE000 E440 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0344 |
0xE000 E444 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0348 |
0xE000 E448 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 034C |
0xE000 E44C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0350 |
0xE000 E450 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0354 |
0xE000 E454 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0358 |
0xE000 E458 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 035C |
0xE000 E45C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0360 |
0xE000 E460 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0364 |
0xE000 E464 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0368 |
0xE000 E468 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 036C |
0xE000 E46C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0370 |
0xE000 E470 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0374 |
0xE000 E474 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0378 |
0xE000 E478 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 037C |
0xE000 E47C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0380 |
0xE000 E480 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0384 |
0xE000 E484 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0388 |
0xE000 E488 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 038C |
0xE000 E48C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0390 |
0xE000 E490 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0394 |
0xE000 E494 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0398 |
0xE000 E498 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 039C |
0xE000 E49C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03A0 |
0xE000 E4A0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03A4 |
0xE000 E4A4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03A8 |
0xE000 E4A8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03AC |
0xE000 E4AC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03B0 |
0xE000 E4B0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03B4 |
0xE000 E4B4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03B8 |
0xE000 E4B8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03BC |
0xE000 E4BC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03C0 |
0xE000 E4C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03C4 |
0xE000 E4C4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03C8 |
0xE000 E4C8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03CC |
0xE000 E4CC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03D0 |
0xE000 E4D0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03D4 |
0xE000 E4D4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03D8 |
0xE000 E4D8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03DC |
0xE000 E4DC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03E0 |
0xE000 E4E0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03E4 |
0xE000 E4E4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03E8 |
0xE000 E4E8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03EC |
0xE000 E4EC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03F0 |
0xE000 E4F0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03F4 |
0xE000 E4F4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03F8 |
0xE000 E4F8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 03FC |
0xE000 E4FC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0xE000 E500 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0xE000 E504 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0408 |
0xE000 E508 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 040C |
0xE000 E50C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0410 |
0xE000 E510 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0414 |
0xE000 E514 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0418 |
0xE000 E518 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 041C |
0xE000 E51C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0420 |
0xE000 E520 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0424 |
0xE000 E524 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0428 |
0xE000 E528 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 042C |
0xE000 E52C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0430 |
0xE000 E530 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0434 |
0xE000 E534 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0438 |
0xE000 E538 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 043C |
0xE000 E53C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0440 |
0xE000 E540 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0444 |
0xE000 E544 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 E100 | Instance | 0xE000 E100 |
| Description | Enables or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETENA | For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 E104 | Instance | 0xE000 E104 |
| Description | Enables or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETENA | For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 E108 | Instance | 0xE000 E108 |
| Description | Enables or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETENA | For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0080 | ||
| Physical Address | 0xE000 E180 | Instance | 0xE000 E180 |
| Description | Clears or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRENA | For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0084 | ||
| Physical Address | 0xE000 E184 | Instance | 0xE000 E184 |
| Description | Clears or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRENA | For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0088 | ||
| Physical Address | 0xE000 E188 | Instance | 0xE000 E188 |
| Description | Clears or reads the enabled state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRENA | For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0100 | ||
| Physical Address | 0xE000 E200 | Instance | 0xE000 E200 |
| Description | Enables or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETPEND | For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0104 | ||
| Physical Address | 0xE000 E204 | Instance | 0xE000 E204 |
| Description | Enables or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETPEND | For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0108 | ||
| Physical Address | 0xE000 E208 | Instance | 0xE000 E208 |
| Description | Enables or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | SETPEND | For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0180 | ||
| Physical Address | 0xE000 E280 | Instance | 0xE000 E280 |
| Description | Clears or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRPEND | For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0184 | ||
| Physical Address | 0xE000 E284 | Instance | 0xE000 E284 |
| Description | Clears or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRPEND | For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0188 | ||
| Physical Address | 0xE000 E288 | Instance | 0xE000 E288 |
| Description | Clears or reads the pending state of each group of 32 interrupts | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CLRPEND | For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0200 | ||
| Physical Address | 0xE000 E300 | Instance | 0xE000 E300 |
| Description | For each group of 32 interrupts, shows the active state of each interrupt | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ACTIVE | For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0204 | ||
| Physical Address | 0xE000 E304 | Instance | 0xE000 E304 |
| Description | For each group of 32 interrupts, shows the active state of each interrupt | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ACTIVE | For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0208 | ||
| Physical Address | 0xE000 E308 | Instance | 0xE000 E308 |
| Description | For each group of 32 interrupts, shows the active state of each interrupt | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ACTIVE | For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0280 | ||
| Physical Address | 0xE000 E380 | Instance | 0xE000 E380 |
| Description | For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ITNS | For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0284 | ||
| Physical Address | 0xE000 E384 | Instance | 0xE000 E384 |
| Description | For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ITNS | For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0288 | ||
| Physical Address | 0xE000 E388 | Instance | 0xE000 E388 |
| Description | For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ITNS | For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0300 | ||
| Physical Address | 0xE000 E400 | Instance | 0xE000 E400 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*0, `IAAMO the priority of interrupt number 4*0+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*0, `IAAMO the priority of interrupt number 4*0+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*0, `IAAMO the priority of interrupt number 4*0+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*0, `IAAMO the priority of interrupt number 4*0+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0304 | ||
| Physical Address | 0xE000 E404 | Instance | 0xE000 E404 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*1, `IAAMO the priority of interrupt number 4*1+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*1, `IAAMO the priority of interrupt number 4*1+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*1, `IAAMO the priority of interrupt number 4*1+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*1, `IAAMO the priority of interrupt number 4*1+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0308 | ||
| Physical Address | 0xE000 E408 | Instance | 0xE000 E408 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*2, `IAAMO the priority of interrupt number 4*2+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*2, `IAAMO the priority of interrupt number 4*2+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*2, `IAAMO the priority of interrupt number 4*2+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*2, `IAAMO the priority of interrupt number 4*2+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 030C | ||
| Physical Address | 0xE000 E40C | Instance | 0xE000 E40C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*3, `IAAMO the priority of interrupt number 4*3+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*3, `IAAMO the priority of interrupt number 4*3+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*3, `IAAMO the priority of interrupt number 4*3+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*3, `IAAMO the priority of interrupt number 4*3+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0310 | ||
| Physical Address | 0xE000 E410 | Instance | 0xE000 E410 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*4, `IAAMO the priority of interrupt number 4*4+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*4, `IAAMO the priority of interrupt number 4*4+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*4, `IAAMO the priority of interrupt number 4*4+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*4, `IAAMO the priority of interrupt number 4*4+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0314 | ||
| Physical Address | 0xE000 E414 | Instance | 0xE000 E414 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*5, `IAAMO the priority of interrupt number 4*5+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*5, `IAAMO the priority of interrupt number 4*5+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*5, `IAAMO the priority of interrupt number 4*5+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*5, `IAAMO the priority of interrupt number 4*5+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0318 | ||
| Physical Address | 0xE000 E418 | Instance | 0xE000 E418 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*6, `IAAMO the priority of interrupt number 4*6+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*6, `IAAMO the priority of interrupt number 4*6+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*6, `IAAMO the priority of interrupt number 4*6+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*6, `IAAMO the priority of interrupt number 4*6+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 031C | ||
| Physical Address | 0xE000 E41C | Instance | 0xE000 E41C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*7, `IAAMO the priority of interrupt number 4*7+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*7, `IAAMO the priority of interrupt number 4*7+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*7, `IAAMO the priority of interrupt number 4*7+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*7, `IAAMO the priority of interrupt number 4*7+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0320 | ||
| Physical Address | 0xE000 E420 | Instance | 0xE000 E420 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*8, `IAAMO the priority of interrupt number 4*8+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*8, `IAAMO the priority of interrupt number 4*8+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*8, `IAAMO the priority of interrupt number 4*8+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*8, `IAAMO the priority of interrupt number 4*8+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0324 | ||
| Physical Address | 0xE000 E424 | Instance | 0xE000 E424 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*9, `IAAMO the priority of interrupt number 4*9+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*9, `IAAMO the priority of interrupt number 4*9+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*9, `IAAMO the priority of interrupt number 4*9+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*9, `IAAMO the priority of interrupt number 4*9+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0328 | ||
| Physical Address | 0xE000 E428 | Instance | 0xE000 E428 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*10, `IAAMO the priority of interrupt number 4*10+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*10, `IAAMO the priority of interrupt number 4*10+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*10, `IAAMO the priority of interrupt number 4*10+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*10, `IAAMO the priority of interrupt number 4*10+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 032C | ||
| Physical Address | 0xE000 E42C | Instance | 0xE000 E42C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*11, `IAAMO the priority of interrupt number 4*11+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*11, `IAAMO the priority of interrupt number 4*11+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*11, `IAAMO the priority of interrupt number 4*11+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*11, `IAAMO the priority of interrupt number 4*11+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0330 | ||
| Physical Address | 0xE000 E430 | Instance | 0xE000 E430 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*12, `IAAMO the priority of interrupt number 4*12+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*12, `IAAMO the priority of interrupt number 4*12+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*12, `IAAMO the priority of interrupt number 4*12+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*12, `IAAMO the priority of interrupt number 4*12+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0334 | ||
| Physical Address | 0xE000 E434 | Instance | 0xE000 E434 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*13, `IAAMO the priority of interrupt number 4*13+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*13, `IAAMO the priority of interrupt number 4*13+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*13, `IAAMO the priority of interrupt number 4*13+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*13, `IAAMO the priority of interrupt number 4*13+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0338 | ||
| Physical Address | 0xE000 E438 | Instance | 0xE000 E438 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*14, `IAAMO the priority of interrupt number 4*14+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*14, `IAAMO the priority of interrupt number 4*14+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*14, `IAAMO the priority of interrupt number 4*14+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*14, `IAAMO the priority of interrupt number 4*14+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 033C | ||
| Physical Address | 0xE000 E43C | Instance | 0xE000 E43C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*15, `IAAMO the priority of interrupt number 4*15+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*15, `IAAMO the priority of interrupt number 4*15+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*15, `IAAMO the priority of interrupt number 4*15+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*15, `IAAMO the priority of interrupt number 4*15+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0340 | ||
| Physical Address | 0xE000 E440 | Instance | 0xE000 E440 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*16, `IAAMO the priority of interrupt number 4*16+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*16, `IAAMO the priority of interrupt number 4*16+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*16, `IAAMO the priority of interrupt number 4*16+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*16, `IAAMO the priority of interrupt number 4*16+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0344 | ||
| Physical Address | 0xE000 E444 | Instance | 0xE000 E444 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*17, `IAAMO the priority of interrupt number 4*17+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*17, `IAAMO the priority of interrupt number 4*17+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*17, `IAAMO the priority of interrupt number 4*17+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*17, `IAAMO the priority of interrupt number 4*17+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0348 | ||
| Physical Address | 0xE000 E448 | Instance | 0xE000 E448 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*18, `IAAMO the priority of interrupt number 4*18+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*18, `IAAMO the priority of interrupt number 4*18+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*18, `IAAMO the priority of interrupt number 4*18+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*18, `IAAMO the priority of interrupt number 4*18+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 034C | ||
| Physical Address | 0xE000 E44C | Instance | 0xE000 E44C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*19, `IAAMO the priority of interrupt number 4*19+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*19, `IAAMO the priority of interrupt number 4*19+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*19, `IAAMO the priority of interrupt number 4*19+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*19, `IAAMO the priority of interrupt number 4*19+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0350 | ||
| Physical Address | 0xE000 E450 | Instance | 0xE000 E450 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*20, `IAAMO the priority of interrupt number 4*20+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*20, `IAAMO the priority of interrupt number 4*20+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*20, `IAAMO the priority of interrupt number 4*20+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*20, `IAAMO the priority of interrupt number 4*20+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0354 | ||
| Physical Address | 0xE000 E454 | Instance | 0xE000 E454 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*21, `IAAMO the priority of interrupt number 4*21+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*21, `IAAMO the priority of interrupt number 4*21+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*21, `IAAMO the priority of interrupt number 4*21+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*21, `IAAMO the priority of interrupt number 4*21+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0358 | ||
| Physical Address | 0xE000 E458 | Instance | 0xE000 E458 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*22, `IAAMO the priority of interrupt number 4*22+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*22, `IAAMO the priority of interrupt number 4*22+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*22, `IAAMO the priority of interrupt number 4*22+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*22, `IAAMO the priority of interrupt number 4*22+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 035C | ||
| Physical Address | 0xE000 E45C | Instance | 0xE000 E45C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*23, `IAAMO the priority of interrupt number 4*23+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*23, `IAAMO the priority of interrupt number 4*23+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*23, `IAAMO the priority of interrupt number 4*23+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*23, `IAAMO the priority of interrupt number 4*23+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0360 | ||
| Physical Address | 0xE000 E460 | Instance | 0xE000 E460 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*24, `IAAMO the priority of interrupt number 4*24+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*24, `IAAMO the priority of interrupt number 4*24+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*24, `IAAMO the priority of interrupt number 4*24+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*24, `IAAMO the priority of interrupt number 4*24+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0364 | ||
| Physical Address | 0xE000 E464 | Instance | 0xE000 E464 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*25, `IAAMO the priority of interrupt number 4*25+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*25, `IAAMO the priority of interrupt number 4*25+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*25, `IAAMO the priority of interrupt number 4*25+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*25, `IAAMO the priority of interrupt number 4*25+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0368 | ||
| Physical Address | 0xE000 E468 | Instance | 0xE000 E468 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*26, `IAAMO the priority of interrupt number 4*26+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*26, `IAAMO the priority of interrupt number 4*26+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*26, `IAAMO the priority of interrupt number 4*26+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*26, `IAAMO the priority of interrupt number 4*26+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 036C | ||
| Physical Address | 0xE000 E46C | Instance | 0xE000 E46C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*27, `IAAMO the priority of interrupt number 4*27+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*27, `IAAMO the priority of interrupt number 4*27+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*27, `IAAMO the priority of interrupt number 4*27+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*27, `IAAMO the priority of interrupt number 4*27+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0370 | ||
| Physical Address | 0xE000 E470 | Instance | 0xE000 E470 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*28, `IAAMO the priority of interrupt number 4*28+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*28, `IAAMO the priority of interrupt number 4*28+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*28, `IAAMO the priority of interrupt number 4*28+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*28, `IAAMO the priority of interrupt number 4*28+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0374 | ||
| Physical Address | 0xE000 E474 | Instance | 0xE000 E474 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*29, `IAAMO the priority of interrupt number 4*29+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*29, `IAAMO the priority of interrupt number 4*29+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*29, `IAAMO the priority of interrupt number 4*29+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*29, `IAAMO the priority of interrupt number 4*29+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0378 | ||
| Physical Address | 0xE000 E478 | Instance | 0xE000 E478 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*30, `IAAMO the priority of interrupt number 4*30+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*30, `IAAMO the priority of interrupt number 4*30+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*30, `IAAMO the priority of interrupt number 4*30+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*30, `IAAMO the priority of interrupt number 4*30+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 037C | ||
| Physical Address | 0xE000 E47C | Instance | 0xE000 E47C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*31, `IAAMO the priority of interrupt number 4*31+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*31, `IAAMO the priority of interrupt number 4*31+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*31, `IAAMO the priority of interrupt number 4*31+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*31, `IAAMO the priority of interrupt number 4*31+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0380 | ||
| Physical Address | 0xE000 E480 | Instance | 0xE000 E480 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*32, `IAAMO the priority of interrupt number 4*32+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*32, `IAAMO the priority of interrupt number 4*32+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*32, `IAAMO the priority of interrupt number 4*32+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*32, `IAAMO the priority of interrupt number 4*32+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0384 | ||
| Physical Address | 0xE000 E484 | Instance | 0xE000 E484 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*33, `IAAMO the priority of interrupt number 4*33+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*33, `IAAMO the priority of interrupt number 4*33+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*33, `IAAMO the priority of interrupt number 4*33+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*33, `IAAMO the priority of interrupt number 4*33+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0388 | ||
| Physical Address | 0xE000 E488 | Instance | 0xE000 E488 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*34, `IAAMO the priority of interrupt number 4*34+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*34, `IAAMO the priority of interrupt number 4*34+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*34, `IAAMO the priority of interrupt number 4*34+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*34, `IAAMO the priority of interrupt number 4*34+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 038C | ||
| Physical Address | 0xE000 E48C | Instance | 0xE000 E48C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*35, `IAAMO the priority of interrupt number 4*35+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*35, `IAAMO the priority of interrupt number 4*35+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*35, `IAAMO the priority of interrupt number 4*35+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*35, `IAAMO the priority of interrupt number 4*35+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0390 | ||
| Physical Address | 0xE000 E490 | Instance | 0xE000 E490 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*36, `IAAMO the priority of interrupt number 4*36+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*36, `IAAMO the priority of interrupt number 4*36+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*36, `IAAMO the priority of interrupt number 4*36+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*36, `IAAMO the priority of interrupt number 4*36+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0394 | ||
| Physical Address | 0xE000 E494 | Instance | 0xE000 E494 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*37, `IAAMO the priority of interrupt number 4*37+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*37, `IAAMO the priority of interrupt number 4*37+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*37, `IAAMO the priority of interrupt number 4*37+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*37, `IAAMO the priority of interrupt number 4*37+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0398 | ||
| Physical Address | 0xE000 E498 | Instance | 0xE000 E498 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*38, `IAAMO the priority of interrupt number 4*38+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*38, `IAAMO the priority of interrupt number 4*38+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*38, `IAAMO the priority of interrupt number 4*38+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*38, `IAAMO the priority of interrupt number 4*38+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 039C | ||
| Physical Address | 0xE000 E49C | Instance | 0xE000 E49C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*39, `IAAMO the priority of interrupt number 4*39+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*39, `IAAMO the priority of interrupt number 4*39+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*39, `IAAMO the priority of interrupt number 4*39+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*39, `IAAMO the priority of interrupt number 4*39+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03A0 | ||
| Physical Address | 0xE000 E4A0 | Instance | 0xE000 E4A0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*40, `IAAMO the priority of interrupt number 4*40+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*40, `IAAMO the priority of interrupt number 4*40+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*40, `IAAMO the priority of interrupt number 4*40+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*40, `IAAMO the priority of interrupt number 4*40+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03A4 | ||
| Physical Address | 0xE000 E4A4 | Instance | 0xE000 E4A4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*41, `IAAMO the priority of interrupt number 4*41+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*41, `IAAMO the priority of interrupt number 4*41+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*41, `IAAMO the priority of interrupt number 4*41+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*41, `IAAMO the priority of interrupt number 4*41+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03A8 | ||
| Physical Address | 0xE000 E4A8 | Instance | 0xE000 E4A8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*42, `IAAMO the priority of interrupt number 4*42+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*42, `IAAMO the priority of interrupt number 4*42+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*42, `IAAMO the priority of interrupt number 4*42+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*42, `IAAMO the priority of interrupt number 4*42+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03AC | ||
| Physical Address | 0xE000 E4AC | Instance | 0xE000 E4AC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*43, `IAAMO the priority of interrupt number 4*43+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*43, `IAAMO the priority of interrupt number 4*43+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*43, `IAAMO the priority of interrupt number 4*43+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*43, `IAAMO the priority of interrupt number 4*43+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03B0 | ||
| Physical Address | 0xE000 E4B0 | Instance | 0xE000 E4B0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*44, `IAAMO the priority of interrupt number 4*44+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*44, `IAAMO the priority of interrupt number 4*44+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*44, `IAAMO the priority of interrupt number 4*44+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*44, `IAAMO the priority of interrupt number 4*44+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03B4 | ||
| Physical Address | 0xE000 E4B4 | Instance | 0xE000 E4B4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*45, `IAAMO the priority of interrupt number 4*45+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*45, `IAAMO the priority of interrupt number 4*45+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*45, `IAAMO the priority of interrupt number 4*45+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*45, `IAAMO the priority of interrupt number 4*45+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03B8 | ||
| Physical Address | 0xE000 E4B8 | Instance | 0xE000 E4B8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*46, `IAAMO the priority of interrupt number 4*46+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*46, `IAAMO the priority of interrupt number 4*46+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*46, `IAAMO the priority of interrupt number 4*46+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*46, `IAAMO the priority of interrupt number 4*46+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03BC | ||
| Physical Address | 0xE000 E4BC | Instance | 0xE000 E4BC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*47, `IAAMO the priority of interrupt number 4*47+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*47, `IAAMO the priority of interrupt number 4*47+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*47, `IAAMO the priority of interrupt number 4*47+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*47, `IAAMO the priority of interrupt number 4*47+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03C0 | ||
| Physical Address | 0xE000 E4C0 | Instance | 0xE000 E4C0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*48, `IAAMO the priority of interrupt number 4*48+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*48, `IAAMO the priority of interrupt number 4*48+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*48, `IAAMO the priority of interrupt number 4*48+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*48, `IAAMO the priority of interrupt number 4*48+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03C4 | ||
| Physical Address | 0xE000 E4C4 | Instance | 0xE000 E4C4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*49, `IAAMO the priority of interrupt number 4*49+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*49, `IAAMO the priority of interrupt number 4*49+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*49, `IAAMO the priority of interrupt number 4*49+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*49, `IAAMO the priority of interrupt number 4*49+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03C8 | ||
| Physical Address | 0xE000 E4C8 | Instance | 0xE000 E4C8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*50, `IAAMO the priority of interrupt number 4*50+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*50, `IAAMO the priority of interrupt number 4*50+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*50, `IAAMO the priority of interrupt number 4*50+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*50, `IAAMO the priority of interrupt number 4*50+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03CC | ||
| Physical Address | 0xE000 E4CC | Instance | 0xE000 E4CC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*51, `IAAMO the priority of interrupt number 4*51+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*51, `IAAMO the priority of interrupt number 4*51+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*51, `IAAMO the priority of interrupt number 4*51+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*51, `IAAMO the priority of interrupt number 4*51+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03D0 | ||
| Physical Address | 0xE000 E4D0 | Instance | 0xE000 E4D0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*52, `IAAMO the priority of interrupt number 4*52+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*52, `IAAMO the priority of interrupt number 4*52+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*52, `IAAMO the priority of interrupt number 4*52+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*52, `IAAMO the priority of interrupt number 4*52+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03D4 | ||
| Physical Address | 0xE000 E4D4 | Instance | 0xE000 E4D4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*53, `IAAMO the priority of interrupt number 4*53+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*53, `IAAMO the priority of interrupt number 4*53+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*53, `IAAMO the priority of interrupt number 4*53+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*53, `IAAMO the priority of interrupt number 4*53+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03D8 | ||
| Physical Address | 0xE000 E4D8 | Instance | 0xE000 E4D8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*54, `IAAMO the priority of interrupt number 4*54+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*54, `IAAMO the priority of interrupt number 4*54+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*54, `IAAMO the priority of interrupt number 4*54+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*54, `IAAMO the priority of interrupt number 4*54+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03DC | ||
| Physical Address | 0xE000 E4DC | Instance | 0xE000 E4DC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*55, `IAAMO the priority of interrupt number 4*55+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*55, `IAAMO the priority of interrupt number 4*55+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*55, `IAAMO the priority of interrupt number 4*55+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*55, `IAAMO the priority of interrupt number 4*55+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03E0 | ||
| Physical Address | 0xE000 E4E0 | Instance | 0xE000 E4E0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*56, `IAAMO the priority of interrupt number 4*56+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*56, `IAAMO the priority of interrupt number 4*56+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*56, `IAAMO the priority of interrupt number 4*56+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*56, `IAAMO the priority of interrupt number 4*56+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03E4 | ||
| Physical Address | 0xE000 E4E4 | Instance | 0xE000 E4E4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*57, `IAAMO the priority of interrupt number 4*57+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*57, `IAAMO the priority of interrupt number 4*57+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*57, `IAAMO the priority of interrupt number 4*57+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*57, `IAAMO the priority of interrupt number 4*57+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03E8 | ||
| Physical Address | 0xE000 E4E8 | Instance | 0xE000 E4E8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*58, `IAAMO the priority of interrupt number 4*58+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*58, `IAAMO the priority of interrupt number 4*58+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*58, `IAAMO the priority of interrupt number 4*58+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*58, `IAAMO the priority of interrupt number 4*58+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03EC | ||
| Physical Address | 0xE000 E4EC | Instance | 0xE000 E4EC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*59, `IAAMO the priority of interrupt number 4*59+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*59, `IAAMO the priority of interrupt number 4*59+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*59, `IAAMO the priority of interrupt number 4*59+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*59, `IAAMO the priority of interrupt number 4*59+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03F0 | ||
| Physical Address | 0xE000 E4F0 | Instance | 0xE000 E4F0 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*60, `IAAMO the priority of interrupt number 4*60+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*60, `IAAMO the priority of interrupt number 4*60+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*60, `IAAMO the priority of interrupt number 4*60+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*60, `IAAMO the priority of interrupt number 4*60+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03F4 | ||
| Physical Address | 0xE000 E4F4 | Instance | 0xE000 E4F4 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*61, `IAAMO the priority of interrupt number 4*61+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*61, `IAAMO the priority of interrupt number 4*61+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*61, `IAAMO the priority of interrupt number 4*61+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*61, `IAAMO the priority of interrupt number 4*61+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03F8 | ||
| Physical Address | 0xE000 E4F8 | Instance | 0xE000 E4F8 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*62, `IAAMO the priority of interrupt number 4*62+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*62, `IAAMO the priority of interrupt number 4*62+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*62, `IAAMO the priority of interrupt number 4*62+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*62, `IAAMO the priority of interrupt number 4*62+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 03FC | ||
| Physical Address | 0xE000 E4FC | Instance | 0xE000 E4FC |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*63, `IAAMO the priority of interrupt number 4*63+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*63, `IAAMO the priority of interrupt number 4*63+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*63, `IAAMO the priority of interrupt number 4*63+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*63, `IAAMO the priority of interrupt number 4*63+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0xE000 E500 | Instance | 0xE000 E500 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*64, `IAAMO the priority of interrupt number 4*64+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*64, `IAAMO the priority of interrupt number 4*64+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*64, `IAAMO the priority of interrupt number 4*64+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*64, `IAAMO the priority of interrupt number 4*64+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0404 | ||
| Physical Address | 0xE000 E504 | Instance | 0xE000 E504 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*65, `IAAMO the priority of interrupt number 4*65+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*65, `IAAMO the priority of interrupt number 4*65+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*65, `IAAMO the priority of interrupt number 4*65+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*65, `IAAMO the priority of interrupt number 4*65+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0408 | ||
| Physical Address | 0xE000 E508 | Instance | 0xE000 E508 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*66, `IAAMO the priority of interrupt number 4*66+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*66, `IAAMO the priority of interrupt number 4*66+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*66, `IAAMO the priority of interrupt number 4*66+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*66, `IAAMO the priority of interrupt number 4*66+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 040C | ||
| Physical Address | 0xE000 E50C | Instance | 0xE000 E50C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*67, `IAAMO the priority of interrupt number 4*67+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*67, `IAAMO the priority of interrupt number 4*67+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*67, `IAAMO the priority of interrupt number 4*67+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*67, `IAAMO the priority of interrupt number 4*67+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0410 | ||
| Physical Address | 0xE000 E510 | Instance | 0xE000 E510 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*68, `IAAMO the priority of interrupt number 4*68+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*68, `IAAMO the priority of interrupt number 4*68+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*68, `IAAMO the priority of interrupt number 4*68+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*68, `IAAMO the priority of interrupt number 4*68+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0414 | ||
| Physical Address | 0xE000 E514 | Instance | 0xE000 E514 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*69, `IAAMO the priority of interrupt number 4*69+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*69, `IAAMO the priority of interrupt number 4*69+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*69, `IAAMO the priority of interrupt number 4*69+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*69, `IAAMO the priority of interrupt number 4*69+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0418 | ||
| Physical Address | 0xE000 E518 | Instance | 0xE000 E518 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*70, `IAAMO the priority of interrupt number 4*70+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*70, `IAAMO the priority of interrupt number 4*70+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*70, `IAAMO the priority of interrupt number 4*70+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*70, `IAAMO the priority of interrupt number 4*70+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 041C | ||
| Physical Address | 0xE000 E51C | Instance | 0xE000 E51C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*71, `IAAMO the priority of interrupt number 4*71+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*71, `IAAMO the priority of interrupt number 4*71+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*71, `IAAMO the priority of interrupt number 4*71+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*71, `IAAMO the priority of interrupt number 4*71+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0420 | ||
| Physical Address | 0xE000 E520 | Instance | 0xE000 E520 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*72, `IAAMO the priority of interrupt number 4*72+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*72, `IAAMO the priority of interrupt number 4*72+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*72, `IAAMO the priority of interrupt number 4*72+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*72, `IAAMO the priority of interrupt number 4*72+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0424 | ||
| Physical Address | 0xE000 E524 | Instance | 0xE000 E524 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*73, `IAAMO the priority of interrupt number 4*73+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*73, `IAAMO the priority of interrupt number 4*73+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*73, `IAAMO the priority of interrupt number 4*73+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*73, `IAAMO the priority of interrupt number 4*73+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0428 | ||
| Physical Address | 0xE000 E528 | Instance | 0xE000 E528 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*74, `IAAMO the priority of interrupt number 4*74+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*74, `IAAMO the priority of interrupt number 4*74+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*74, `IAAMO the priority of interrupt number 4*74+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*74, `IAAMO the priority of interrupt number 4*74+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 042C | ||
| Physical Address | 0xE000 E52C | Instance | 0xE000 E52C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*75, `IAAMO the priority of interrupt number 4*75+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*75, `IAAMO the priority of interrupt number 4*75+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*75, `IAAMO the priority of interrupt number 4*75+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*75, `IAAMO the priority of interrupt number 4*75+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0430 | ||
| Physical Address | 0xE000 E530 | Instance | 0xE000 E530 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*76, `IAAMO the priority of interrupt number 4*76+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*76, `IAAMO the priority of interrupt number 4*76+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*76, `IAAMO the priority of interrupt number 4*76+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*76, `IAAMO the priority of interrupt number 4*76+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0434 | ||
| Physical Address | 0xE000 E534 | Instance | 0xE000 E534 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*77, `IAAMO the priority of interrupt number 4*77+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*77, `IAAMO the priority of interrupt number 4*77+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*77, `IAAMO the priority of interrupt number 4*77+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*77, `IAAMO the priority of interrupt number 4*77+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0438 | ||
| Physical Address | 0xE000 E538 | Instance | 0xE000 E538 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*78, `IAAMO the priority of interrupt number 4*78+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*78, `IAAMO the priority of interrupt number 4*78+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*78, `IAAMO the priority of interrupt number 4*78+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*78, `IAAMO the priority of interrupt number 4*78+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 043C | ||
| Physical Address | 0xE000 E53C | Instance | 0xE000 E53C |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*79, `IAAMO the priority of interrupt number 4*79+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*79, `IAAMO the priority of interrupt number 4*79+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*79, `IAAMO the priority of interrupt number 4*79+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*79, `IAAMO the priority of interrupt number 4*79+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0440 | ||
| Physical Address | 0xE000 E540 | Instance | 0xE000 E540 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*80, `IAAMO the priority of interrupt number 4*80+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*80, `IAAMO the priority of interrupt number 4*80+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*80, `IAAMO the priority of interrupt number 4*80+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*80, `IAAMO the priority of interrupt number 4*80+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| Address Offset | 0x0000 0444 | ||
| Physical Address | 0xE000 E544 | Instance | 0xE000 E544 |
| Description | Sets or reads interrupt priorities | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | PRI_N3 | For register NVIC_IPR*81, `IAAMO the priority of interrupt number 4*81+3, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 23:16 | PRI_N2 | For register NVIC_IPR*81, `IAAMO the priority of interrupt number 4*81+2, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 15:8 | PRI_N1 | For register NVIC_IPR*81, `IAAMO the priority of interrupt number 4*81+1, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
| 7:0 | PRI_N0 | For register NVIC_IPR*81, `IAAMO the priority of interrupt number 4*81+0, or is RES0 if the PE does not implement this interrupt | RW | 0x00 | ||
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