Instance: CPU_MTB
Component: CPU_MTB
Base address: 0xE0043000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE004 3000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE004 3004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE004 3008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0xE004 300C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE004 3010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE004 3014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0xE004 3020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FBC |
0xE004 3FBC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FC8 |
0xE004 3FC8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FCC |
0xE004 3FCC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD0 |
0xE004 3FD0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD4 |
0xE004 3FD4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD8 |
0xE004 3FD8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FDC |
0xE004 3FDC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE0 |
0xE004 3FE0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE4 |
0xE004 3FE4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE8 |
0xE004 3FE8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FEC |
0xE004 3FEC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF0 |
0xE004 3FF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF4 |
0xE004 3FF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF8 |
0xE004 3FF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FFC |
0xE004 3FFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE004 3000 | Instance | 0xE004 3000 |
| Description | The MTB_POSITION register contains the trace write pointer and the wrap bit. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | POINTER | RW | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||
| 2 | WRAP | RW | 0 | |||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE004 3004 | Instance | 0xE004 3004 |
| Description | The MTB_MASTER register contains the main trace enable bit and other trace control fields. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | EN | RW | 0 | |||
| 30 | NSEN | RW | 0 | |||
| 29:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
| 9 | HALTREQ | RW | 0 | |||
| 8 | RAMPRIV | RW | 0 | |||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6 | TSTOPEN | RW | 0 | |||
| 5 | TSTARTEN | RW | 0 | |||
| 4:0 | MASK | RW | 0b0 0000 | |||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE004 3008 | Instance | 0xE004 3008 |
| Description | The MTB_FLOW register contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:3 | WATERMARK | RW | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||
| 2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 1 | AUTOHALT | RW | 0 | |||
| 0 | AUTOSTOP | RW | 0 | |||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE004 300C | Instance | 0xE004 300C |
| Description | The MTB_BASE register indicates where the SRAM is located in the processor memory map. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | BASE | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||
| 4:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE004 3010 | Instance | 0xE004 3010 |
| Description | The MTB_TSTART register controls the trace start events using the DWT CMPMATCH feature. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | CMPMATCH3 | Reserved, `ImpDefRES0 | RO | 0 | ||
| 2 | CMPMATCH2 | Reserved, `ImpDefRES0 | RO | 0 | ||
| 1 | CMPMATCH1 | RW | 0 | |||
| 0 | CMPMATCH0 | RW | 0 | |||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE004 3014 | Instance | 0xE004 3014 |
| Description | The MTB_TSTOP register controls the trace stop events using the DWT CMPMATCH feature. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | CMPMATCH3 | Reserved, `ImpDefRES0 | RO | 0 | ||
| 2 | CMPMATCH2 | Reserved, `ImpDefRES0 | RO | 0 | ||
| 1 | CMPMATCH1 | RW | 0 | |||
| 0 | CMPMATCH0 | RW | 0 | |||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE004 3020 | Instance | 0xE004 3020 |
| Description | The MTB_SECURE register allows the SRAM region to be partitioned into two regions, with one region being defined as Secure and the other as Non-secure. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | THRESHOLD | RW | 0b000 0000 0000 0000 0000 0000 0000 | |||
| 4:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 1 | NS | RW | 0 | |||
| 0 | THRSEN | RW | 0 | |||
| Address Offset | 0x0000 0FBC | ||
| Physical Address | 0xE004 3FBC | Instance | 0xE004 3FBC |
| Description | MTB_DEVARCH | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:21 | ARCHITECT | reads as 0x23B | RO | 0b000 0000 0000 | ||
| 20 | PRESENT | reads as 0b1 | RO | 0 | ||
| 19:16 | REVISION | reads as 0x0 | RO | 0x0 | ||
| 15:0 | ARCHID | reads as 0x0A31 | RO | 0x0000 | ||
| Address Offset | 0x0000 0FC8 | ||
| Physical Address | 0xE004 3FC8 | Instance | 0xE004 3FC8 |
| Description | MTB_DEVID | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FCC | ||
| Physical Address | 0xE004 3FCC | Instance | 0xE004 3FCC |
| Description | MTB_DEVTYPE | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SUB | reads as 0x3 | RO | 0x0 | ||
| 3:0 | MAJOR | reads as 0x1 | RO | 0x0 | ||
| Address Offset | 0x0000 0FD0 | ||
| Physical Address | 0xE004 3FD0 | Instance | 0xE004 3FD0 |
| Description | MTB_PID4 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SIZE | reads as 0x0 | RO | 0x0 | ||
| 3:0 | DES_2 | reads as 0x4 | RO | 0x0 | ||
| Address Offset | 0x0000 0FD4 | ||
| Physical Address | 0xE004 3FD4 | Instance | 0xE004 3FD4 |
| Description | MTB_PID5 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FD8 | ||
| Physical Address | 0xE004 3FD8 | Instance | 0xE004 3FD8 |
| Description | MTB_PID6 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FDC | ||
| Physical Address | 0xE004 3FDC | Instance | 0xE004 3FDC |
| Description | MTB_PID7 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FE0 | ||
| Physical Address | 0xE004 3FE0 | Instance | 0xE004 3FE0 |
| Description | MTB_PID0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PART_0 | reads as 0x8E | RO | 0x00 | ||
| Address Offset | 0x0000 0FE4 | ||
| Physical Address | 0xE004 3FE4 | Instance | 0xE004 3FE4 |
| Description | MTB_PID1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | DES_0 | reads as 0xB | RO | 0x0 | ||
| 3:0 | PART_1 | reads as 0x9 | RO | 0x0 | ||
| Address Offset | 0x0000 0FE8 | ||
| Physical Address | 0xE004 3FE8 | Instance | 0xE004 3FE8 |
| Description | MTB_PID2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVISION | reads as 0x0 | RO | 0x0 | ||
| 3 | JEDEC | reads as 0b1 | RO | 0 | ||
| 2:0 | DES_1 | reads as 0b011 | RO | 0b000 | ||
| Address Offset | 0x0000 0FEC | ||
| Physical Address | 0xE004 3FEC | Instance | 0xE004 3FEC |
| Description | MTB_PID3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVAND | reads as 0x0 | RO | 0x0 | ||
| 3:0 | CMOD | reads as 0x0 | RO | 0x0 | ||
| Address Offset | 0x0000 0FF0 | ||
| Physical Address | 0xE004 3FF0 | Instance | 0xE004 3FF0 |
| Description | MTB_CID0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | reads as 0x0D | RO | 0x00 | ||
| Address Offset | 0x0000 0FF4 | ||
| Physical Address | 0xE004 3FF4 | Instance | 0xE004 3FF4 |
| Description | MTB_CID1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | CLASS | reads as 0x9 | RO | 0x0 | ||
| 3:0 | PRMBL_1 | reads as 0x0 | RO | 0x0 | ||
| Address Offset | 0x0000 0FF8 | ||
| Physical Address | 0xE004 3FF8 | Instance | 0xE004 3FF8 |
| Description | MTB_CID2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | reads as 0x05 | RO | 0x00 | ||
| Address Offset | 0x0000 0FFC | ||
| Physical Address | 0xE004 3FFC | Instance | 0xE004 3FFC |
| Description | MTB_CID3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | reads as 0xB1 | RO | 0x00 | ||
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