Instance: CPU_MPU
Component: CPU_MPU
Base address: 0xE000EDC0
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0bXXXX XXXX XXXX XXXX XXXX XXXX XXX0 0XX0 |
0x0000 0000 |
0xE000 EDC0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 EDC4 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 EDC0 | Instance | 0xE000 EDC0 |
| Description | Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | Attr3 | Memory attribute encoding for MPU regions with an AttrIndex of 3 | RW | 0x00 | ||
| 23:16 | Attr2 | Memory attribute encoding for MPU regions with an AttrIndex of 2 | RW | 0x00 | ||
| 15:8 | Attr1 | Memory attribute encoding for MPU regions with an AttrIndex of 1 | RW | 0x00 | ||
| 31:5 | LIMIT | Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against | RW | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 4:3 | SH | Defines the Shareability domain of this region for Normal memory | RW | 0b00 | ||
| 2 | PRIVDEFENA | Controls whether the default memory map is enabled for privileged software | RW | 0 | ||
| 3:1 | AttrIndx | Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields | RW | 0b000 | ||
| 7:0 | Attr0 | Memory attribute encoding for MPU regions with an AttrIndex of 0 | RW | 0x00 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 EDC4 | Instance | 0xE000 EDC4 |
| Description | Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | Attr7 | Memory attribute encoding for MPU regions with an AttrIndex of 7 | RW | 0x00 | ||
| 23:16 | Attr6 | Memory attribute encoding for MPU regions with an AttrIndex of 6 | RW | 0x00 | ||
| 15:8 | Attr5 | Memory attribute encoding for MPU regions with an AttrIndex of 5 | RW | 0x00 | ||
| 7:0 | Attr4 | Memory attribute encoding for MPU regions with an AttrIndex of 4 | RW | 0x00 | ||
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