Instance: CPU_ITM
Component: CPU_ITM
Base address: 0xE0000000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 0000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 0004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 0008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0xE000 000C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 0010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 0014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 0018 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0xE000 001C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 0020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 0024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 0028 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0xE000 002C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0xE000 0030 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0xE000 0034 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0xE000 0038 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0xE000 003C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0xE000 0040 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0xE000 0044 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0xE000 0048 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0xE000 004C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0xE000 0050 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0xE000 0054 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0xE000 0058 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0xE000 005C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0xE000 0060 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0xE000 0064 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0068 |
0xE000 0068 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 006C |
0xE000 006C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0070 |
0xE000 0070 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0074 |
0xE000 0074 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0078 |
0xE000 0078 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 007C |
0xE000 007C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0E00 |
0xE000 0E00 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0E40 |
0xE000 0E40 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0E80 |
0xE000 0E80 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0EF0 |
0xE000 0EF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0EF8 |
0xE000 0EF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0F00 |
0xE000 0F00 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FBC |
0xE000 0FBC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FCC |
0xE000 0FCC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD0 |
0xE000 0FD0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD4 |
0xE000 0FD4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD8 |
0xE000 0FD8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FDC |
0xE000 0FDC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE0 |
0xE000 0FE0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE4 |
0xE000 0FE4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE8 |
0xE000 0FE8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FEC |
0xE000 0FEC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF0 |
0xE000 0FF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF4 |
0xE000 0FF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF8 |
0xE000 0FF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FFC |
0xE000 0FFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 0000 | Instance | 0xE000 0000 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 0004 | Instance | 0xE000 0004 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 0008 | Instance | 0xE000 0008 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 000C | Instance | 0xE000 000C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 0010 | Instance | 0xE000 0010 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 0014 | Instance | 0xE000 0014 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 0018 | Instance | 0xE000 0018 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 001C | Instance | 0xE000 001C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 0020 | Instance | 0xE000 0020 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE000 0024 | Instance | 0xE000 0024 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 0028 | Instance | 0xE000 0028 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE000 002C | Instance | 0xE000 002C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 0030 | Instance | 0xE000 0030 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE000 0034 | Instance | 0xE000 0034 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 0038 | Instance | 0xE000 0038 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0xE000 003C | Instance | 0xE000 003C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0xE000 0040 | Instance | 0xE000 0040 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0xE000 0044 | Instance | 0xE000 0044 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0xE000 0048 | Instance | 0xE000 0048 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 004C | ||
| Physical Address | 0xE000 004C | Instance | 0xE000 004C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0050 | ||
| Physical Address | 0xE000 0050 | Instance | 0xE000 0050 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0054 | ||
| Physical Address | 0xE000 0054 | Instance | 0xE000 0054 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0058 | ||
| Physical Address | 0xE000 0058 | Instance | 0xE000 0058 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 005C | ||
| Physical Address | 0xE000 005C | Instance | 0xE000 005C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0060 | ||
| Physical Address | 0xE000 0060 | Instance | 0xE000 0060 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0064 | ||
| Physical Address | 0xE000 0064 | Instance | 0xE000 0064 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0068 | ||
| Physical Address | 0xE000 0068 | Instance | 0xE000 0068 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 006C | ||
| Physical Address | 0xE000 006C | Instance | 0xE000 006C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0070 | ||
| Physical Address | 0xE000 0070 | Instance | 0xE000 0070 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0074 | ||
| Physical Address | 0xE000 0074 | Instance | 0xE000 0074 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0078 | ||
| Physical Address | 0xE000 0078 | Instance | 0xE000 0078 |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 007C | ||
| Physical Address | 0xE000 007C | Instance | 0xE000 007C |
| Description | Provides the interface for generating Instrumentation packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | DISABLED | Indicates whether the Stimulus Port is enabled or disabled | RO | 0 | ||
| 0 | FIFOREADY | Indicates whether the Stimulus Port can accept data | RO | 0 | ||
| Address Offset | 0x0000 0E00 | ||
| Physical Address | 0xE000 0E00 | Instance | 0xE000 0E00 |
| Description | Provide an individual enable bit for each ITM_STIM register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | STIMENA | For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0E40 | ||
| Physical Address | 0xE000 0E40 | Instance | 0xE000 0E40 |
| Description | Controls which stimulus ports can be accessed by unprivileged code | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | PRIVMASK | For PRIVMASK[m], defines the access permissions of ITM_STIM Stimulus Ports 8m to 8m+7 inclusive | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0E80 | ||
| Physical Address | 0xE000 0E80 | Instance | 0xE000 0E80 |
| Description | Configures and controls transfers through the ITM interface | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 23 | BUSY | Indicates whether the ITM is currently processing events | RO | 0 | ||
| 22:16 | TraceBusID | Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field | RW | 0b000 0000 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11:10 | GTSFREQ | Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps | RW | 0b00 | ||
| 9:8 | TSPrescale | Local timestamp prescaler, used with the trace packet reference clock | RW | 0b00 | ||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 5 | STALLENA | Stall the PE to guarantee delivery of Data Trace packets. | RW | 0 | ||
| 4 | SWOENA | Enables asynchronous clocking of the timestamp counter | RW | 0 | ||
| 3 | TXENA | Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU | RW | 0 | ||
| 2 | SYNCENA | Enables Synchronization packet transmission for a synchronous TPIU | RW | 0 | ||
| 1 | TSENA | Enables Local timestamp generation | RW | 0 | ||
| 0 | ITMENA | Enables the ITM | RW | 0 | ||
| Address Offset | 0x0000 0EF0 | ||
| Physical Address | 0xE000 0EF0 | Instance | 0xE000 0EF0 |
| Description | Integration Mode: Read ATB Ready | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | AFVALID | A read of this bit returns the value of AFVALID | RO | 0 | ||
| 0 | ATREADY | A read of this bit returns the value of ATREADY | RO | 0 | ||
| Address Offset | 0x0000 0EF8 | ||
| Physical Address | 0xE000 0EF8 | Instance | 0xE000 0EF8 |
| Description | Integration Mode: Write ATB Valid | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | AFREADY | A write to this bit gives the value of AFREADY | WO | 0 | ||
| 0 | ATREADY | A write to this bit gives the value of ATVALID | WO | 0 | ||
| Address Offset | 0x0000 0F00 | ||
| Physical Address | 0xE000 0F00 | Instance | 0xE000 0F00 |
| Description | Integration Mode Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | IME | Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. | RW | 0 | ||
| Address Offset | 0x0000 0FBC | ||
| Physical Address | 0xE000 0FBC | Instance | 0xE000 0FBC |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:21 | ARCHITECT | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. | RO | 0b000 0000 0000 | ||
| 20 | PRESENT | Defines that the DEVARCH register is present | RO | 0 | ||
| 19:16 | REVISION | Defines the architecture revision of the component | RO | 0x0 | ||
| 15:12 | ARCHVER | Defines the architecture version of the component | RO | 0x0 | ||
| 11:0 | ARCHPART | Defines the architecture of the component | RO | 0x000 | ||
| Address Offset | 0x0000 0FCC | ||
| Physical Address | 0xE000 0FCC | Instance | 0xE000 0FCC |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SUB | Component sub-type | RO | 0x0 | ||
| 3:0 | MAJOR | Component major type | RO | 0x0 | ||
| Address Offset | 0x0000 0FD0 | ||
| Physical Address | 0xE000 0FD0 | Instance | 0xE000 0FD0 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SIZE | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | DES_2 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FD4 | ||
| Physical Address | 0xE000 0FD4 | Instance | 0xE000 0FD4 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FD8 | ||
| Physical Address | 0xE000 0FD8 | Instance | 0xE000 0FD8 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FDC | ||
| Physical Address | 0xE000 0FDC | Instance | 0xE000 0FDC |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FE0 | ||
| Physical Address | 0xE000 0FE0 | Instance | 0xE000 0FE0 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PART_0 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FE4 | ||
| Physical Address | 0xE000 0FE4 | Instance | 0xE000 0FE4 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | DES_0 | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | PART_1 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FE8 | ||
| Physical Address | 0xE000 0FE8 | Instance | 0xE000 0FE8 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVISION | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3 | JEDEC | See CoreSight Architecture Specification | RO | 0 | ||
| 2:0 | DES_1 | See CoreSight Architecture Specification | RO | 0b000 | ||
| Address Offset | 0x0000 0FEC | ||
| Physical Address | 0xE000 0FEC | Instance | 0xE000 0FEC |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVAND | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | CMOD | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FF0 | ||
| Physical Address | 0xE000 0FF0 | Instance | 0xE000 0FF0 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FF4 | ||
| Physical Address | 0xE000 0FF4 | Instance | 0xE000 0FF4 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | CLASS | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | PRMBL_1 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FF8 | ||
| Physical Address | 0xE000 0FF8 | Instance | 0xE000 0FF8 |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FFC | ||
| Physical Address | 0xE000 0FFC | Instance | 0xE000 0FFC |
| Description | Provides CoreSight discovery information for the ITM | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | See CoreSight Architecture Specification | RO | 0x00 | ||
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