Instance: CPU_ETM
Component: CPU_ETM
Base address: 0xE0041000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE004 1004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0xE004 100C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE004 1010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0xE004 1020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0xE004 1024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0xE004 102C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0xE004 1030 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0xE004 1034 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0xE004 1038 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0xE004 1080 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0140 |
0xE004 1140 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0144 |
0xE004 1144 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0148 |
0xE004 1148 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0180 |
0xE004 1180 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0184 |
0xE004 1184 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0188 |
0xE004 1188 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 018C |
0xE004 118C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0190 |
0xE004 1190 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0194 |
0xE004 1194 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01C0 |
0xE004 11C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01C4 |
0xE004 11C4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01C8 |
0xE004 11C8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01CC |
0xE004 11CC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01D0 |
0xE004 11D0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01D4 |
0xE004 11D4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01D8 |
0xE004 11D8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01E0 |
0xE004 11E0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01E4 |
0xE004 11E4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01E8 |
0xE004 11E8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01EC |
0xE004 11EC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01F0 |
0xE004 11F0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01F4 |
0xE004 11F4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01F8 |
0xE004 11F8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 01FC |
0xE004 11FC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0208 |
0xE004 1208 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 020C |
0xE004 120C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02A0 |
0xE004 12A0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02A4 |
0xE004 12A4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02A8 |
0xE004 12A8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02AC |
0xE004 12AC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02B0 |
0xE004 12B0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02B4 |
0xE004 12B4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02B8 |
0xE004 12B8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02C0 |
0xE004 12C0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02C4 |
0xE004 12C4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02C8 |
0xE004 12C8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02CC |
0xE004 12CC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02D0 |
0xE004 12D0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02D4 |
0xE004 12D4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 02D8 |
0xE004 12D8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0310 |
0xE004 1310 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0314 |
0xE004 1314 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0EE4 |
0xE004 1EE4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0EF4 |
0xE004 1EF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0EFC |
0xE004 1EFC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FA0 |
0xE004 1FA0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FA4 |
0xE004 1FA4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FB8 |
0xE004 1FB8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FBC |
0xE004 1FBC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FC8 |
0xE004 1FC8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FCC |
0xE004 1FCC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD0 |
0xE004 1FD0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD4 |
0xE004 1FD4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD8 |
0xE004 1FD8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FDC |
0xE004 1FDC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE0 |
0xE004 1FE0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE4 |
0xE004 1FE4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE8 |
0xE004 1FE8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FEC |
0xE004 1FEC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF0 |
0xE004 1FF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF4 |
0xE004 1FF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF8 |
0xE004 1FF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FFC |
0xE004 1FFC |
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE004 1004 | Instance | 0xE004 1004 |
| Description | Programming Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EN | Trace Unit Enable | RW | 0 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE004 100C | Instance | 0xE004 100C |
| Description | The TRCSTATR indicates the ETM-Teal status | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PMSTABLE | Indicates whether the ETM-Teal registers are stable and can be read | RO | 0 | ||
| 0 | IDLE | Indicates that the trace unit is inactive | RO | 0 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE004 1010 | Instance | 0xE004 1010 |
| Description | The TRCCONFIGR sets the basic tracing options for the trace unit | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||
| 17 | DV | Reserved, `ImpDefRES0 | RO | 0 | ||
| 16 | DA | Reserved, `ImpDefRES0 | RO | 0 | ||
| 15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 14:13 | QE | Reserved, `ImpDefRES0 | RO | 0b00 | ||
| 12 | RS | Reserved, `ImpDefRES0 | RO | 0 | ||
| 11 | TS | Reserved, `ImpDefRES0 | RO | 0 | ||
| 10:8 | COND | Reserved, `ImpDefRES0 | RO | 0b000 | ||
| 7 | VMID | Reserved, `ImpDefRES0 | RO | 0 | ||
| 6 | CID | Reserved, `ImpDefRES0 | RO | 0 | ||
| 5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 4 | CCI | Reserved, `ImpDefRES0 | RO | 0 | ||
| 3 | BB | Reserved, `ImpDefRES0 | RO | 0 | ||
| 2:1 | INSTP0 | Reserved, `ImpDefRES0 | RO | 0b00 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE004 1020 | Instance | 0xE004 1020 |
| Description | The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15 | TYPE1 | Selects the resource type for event 1 | RW | 0 | ||
| 14:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 10:8 | SEL1 | Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] | RW | 0b000 | ||
| 7 | TYPE0 | Selects the resource type for event 0 | RW | 0 | ||
| 6:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 2:0 | SEL0 | Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] | RW | 0b000 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0xE004 1024 | Instance | 0xE004 1024 |
| Description | The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 | ||
| 12 | LPOVERRIDE | Low power state behavior override | RW | 0 | ||
| 11 | ATB | ATB enabled | RW | 0 | ||
| 10:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 1 | INSTEN1 | One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs | RW | 0 | ||
| 0 | INSTEN0 | One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs | RW | 0 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0xE004 102C | Instance | 0xE004 102C |
| Description | The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | ||
| 10 | INSTPRIORITY | Prioritize instruction trace if instruction trace buffer space is less than LEVEL | RW | 0 | ||
| 9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 8 | ISTALL | Stall processor based on instruction trace buffer space | RW | 0 | ||
| 7:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 3:0 | LEVEL | Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow | RW | 0x0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE004 1030 | Instance | 0xE004 1030 |
| Description | The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | EVENT | An event selector. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams | RW | 0x00 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0xE004 1034 | Instance | 0xE004 1034 |
| Description | The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4:0 | PERIOD | Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes | RO | 0b0 0000 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE004 1038 | Instance | 0xE004 1038 |
| Description | The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | ||
| 11:0 | THRESHOLD | Instruction trace cycle count threshold | RW | 0x000 | ||
| Address Offset | 0x0000 0080 | ||
| Physical Address | 0xE004 1080 | Instance | 0xE004 1080 |
| Description | The TRCVICTLR controls instruction trace filtering | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 19 | EXLEVEL_S3 | In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level | RW | 0 | ||
| 18:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 16 | EXLEVEL_S0 | In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level | RW | 0 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11 | TRCERR | Selects whether a system error exception must always be traced | RW | 0 | ||
| 10 | TRCRESET | Selects whether a reset exception must always be traced | RW | 0 | ||
| 9 | SSSTATUS | Indicates the current status of the start/stop logic | RW | 0 | ||
| 8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 7:0 | EVENT | An event selector | RW | 0x00 | ||
| Address Offset | 0x0000 0140 | ||
| Physical Address | 0xE004 1140 | Instance | 0xE004 1140 |
| Description | The TRCCNTRLDVR defines the reload value for the reduced function counter | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs | RW | 0x0000 | ||
| Address Offset | 0x0000 0144 | ||
| Physical Address | 0xE004 1144 | Instance | 0xE004 1144 |
| Description | The TRCCNTRLDVR defines the reload value for the reduced function counter | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs | RW | 0x0000 | ||
| Address Offset | 0x0000 0148 | ||
| Physical Address | 0xE004 1148 | Instance | 0xE004 1148 |
| Description | The TRCCNTRLDVR defines the reload value for the reduced function counter | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:0 | VALUE | Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs | RW | 0x0000 | ||
| Address Offset | 0x0000 0180 | ||
| Physical Address | 0xE004 1180 | Instance | 0xE004 1180 |
| Description | TRCIDR8 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MAXSPEC | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0184 | ||
| Physical Address | 0xE004 1184 | Instance | 0xE004 1184 |
| Description | TRCIDR9 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | NUMP0KEY | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0188 | ||
| Physical Address | 0xE004 1188 | Instance | 0xE004 1188 |
| Description | TRCIDR10 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | NUMP1KEY | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 018C | ||
| Physical Address | 0xE004 118C | Instance | 0xE004 118C |
| Description | TRCIDR11 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | NUMP1SPC | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0190 | ||
| Physical Address | 0xE004 1190 | Instance | 0xE004 1190 |
| Description | TRCIDR12 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | NUMCONDKEY | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0194 | ||
| Physical Address | 0xE004 1194 | Instance | 0xE004 1194 |
| Description | TRCIDR13 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | NUMCONDSPC | reads as `ImpDef | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 01C0 | ||
| Physical Address | 0xE004 11C0 | Instance | 0xE004 11C0 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01C4 | ||
| Physical Address | 0xE004 11C4 | Instance | 0xE004 11C4 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01C8 | ||
| Physical Address | 0xE004 11C8 | Instance | 0xE004 11C8 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01CC | ||
| Physical Address | 0xE004 11CC | Instance | 0xE004 11CC |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01D0 | ||
| Physical Address | 0xE004 11D0 | Instance | 0xE004 11D0 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01D4 | ||
| Physical Address | 0xE004 11D4 | Instance | 0xE004 11D4 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01D8 | ||
| Physical Address | 0xE004 11D8 | Instance | 0xE004 11D8 |
| Description | The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3:0 | SUPPORT | Set to 0. No IMPLEMENTATION SPECIFIC extensions are supported | RW | 0x0 | ||
| Address Offset | 0x0000 01E0 | ||
| Physical Address | 0xE004 11E0 | Instance | 0xE004 11E0 |
| Description | TRCIDR0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 29 | COMMOPT | reads as `ImpDef | RO | 0 | ||
| 28:24 | TSSIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| 23:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 17 | TRCEXDATA | reads as `ImpDef | RO | 0 | ||
| 16:15 | QSUPP | reads as `ImpDef | RO | 0b00 | ||
| 14 | QFILT | reads as `ImpDef | RO | 0 | ||
| 13:12 | CONDTYPE | reads as `ImpDef | RO | 0b00 | ||
| 11:10 | NUMEVENT | reads as `ImpDef | RO | 0b00 | ||
| 9 | RETSTACK | reads as `ImpDef | RO | 0 | ||
| 8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 7 | TRCCCI | reads as `ImpDef | RO | 0 | ||
| 6 | TRCCOND | reads as `ImpDef | RO | 0 | ||
| 5 | TRCBB | reads as `ImpDef | RO | 0 | ||
| 4:3 | TRCDATA | reads as `ImpDef | RO | 0b00 | ||
| 2:1 | INSTP0 | reads as `ImpDef | RO | 0b00 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 01E4 | ||
| Physical Address | 0xE004 11E4 | Instance | 0xE004 11E4 |
| Description | TRCIDR1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:24 | DESIGNER | reads as `ImpDef | RO | 0x00 | ||
| 23:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11:8 | TRCARCHMAJ | reads as 0b0100 | RO | 0x0 | ||
| 7:4 | TRCARCHMIN | reads as 0b0000 | RO | 0x0 | ||
| 3:0 | REVISION | reads as `ImpDef | RO | 0x0 | ||
| Address Offset | 0x0000 01E8 | ||
| Physical Address | 0xE004 11E8 | Instance | 0xE004 11E8 |
| Description | TRCIDR2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | RESERVED29 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 28:25 | CCSIZE | reads as `ImpDef | RO | 0x0 | ||
| 24:20 | DVSIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| 19:15 | DASIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| 14:10 | VMIDSIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| 9:5 | CIDSIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| 4:0 | IASIZE | reads as `ImpDef | RO | 0b0 0000 | ||
| Address Offset | 0x0000 01EC | ||
| Physical Address | 0xE004 11EC | Instance | 0xE004 11EC |
| Description | TRCIDR3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | NOOVERFLOW | reads as `ImpDef | RO | 0 | ||
| 30:28 | NUMPROC | reads as `ImpDef | RO | 0b000 | ||
| 27 | SYSSTALL | reads as `ImpDef | RO | 0 | ||
| 26 | STALLCTL | reads as `ImpDef | RO | 0 | ||
| 25 | SYNCPR | reads as `ImpDef | RO | 0 | ||
| 24 | TRCERR | reads as `ImpDef | RO | 0 | ||
| 23:20 | EXLEVEL_NS | reads as `ImpDef | RO | 0x0 | ||
| 19:16 | EXLEVEL_S | reads as `ImpDef | RO | 0x0 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11:0 | CCITMIN | reads as `ImpDef | RO | 0x000 | ||
| Address Offset | 0x0000 01F0 | ||
| Physical Address | 0xE004 11F0 | Instance | 0xE004 11F0 |
| Description | TRCIDR4 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | NUMVMIDC | reads as `ImpDef | RO | 0x0 | ||
| 27:24 | NUMCIDC | reads as `ImpDef | RO | 0x0 | ||
| 23:20 | NUMSSCC | reads as `ImpDef | RO | 0x0 | ||
| 19:16 | NUMRSPAIR | reads as `ImpDef | RO | 0x0 | ||
| 15:12 | NUMPC | reads as `ImpDef | RO | 0x0 | ||
| 11:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 8 | SUPPDAC | reads as `ImpDef | RO | 0 | ||
| 7:4 | NUMDVC | reads as `ImpDef | RO | 0x0 | ||
| 3:0 | NUMACPAIRS | reads as `ImpDef | RO | 0x0 | ||
| Address Offset | 0x0000 01F4 | ||
| Physical Address | 0xE004 11F4 | Instance | 0xE004 11F4 |
| Description | TRCIDR5 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | REDFUNCNTR | reads as `ImpDef | RO | 0 | ||
| 30:28 | NUMCNTR | reads as `ImpDef | RO | 0b000 | ||
| 27:25 | NUMSEQSTATE | reads as `ImpDef | RO | 0b000 | ||
| 24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 23 | LPOVERRIDE | reads as `ImpDef | RO | 0 | ||
| 22 | ATBTRIG | reads as `ImpDef | RO | 0 | ||
| 21:16 | TRACEIDSIZE | reads as 0x07 | RO | 0b00 0000 | ||
| 15:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 11:9 | NUMEXTINSEL | reads as `ImpDef | RO | 0b000 | ||
| 8:0 | NUMEXTIN | reads as `ImpDef | RO | 0b0 0000 0000 | ||
| Address Offset | 0x0000 01F8 | ||
| Physical Address | 0xE004 11F8 | Instance | 0xE004 11F8 |
| Description | TRCIDR6 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 01FC | ||
| Physical Address | 0xE004 11FC | Instance | 0xE004 11FC |
| Description | TRCIDR7 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0208 | ||
| Physical Address | 0xE004 1208 | Instance | 0xE004 1208 |
| Description | The TRCRSCTLR controls the trace resources | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||
| 21 | PAIRINV | Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors | RW | 0 | ||
| 20 | INV | Inverts the selected resources | RW | 0 | ||
| 19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 18:16 | GROUP | Selects a group of resource | RW | 0b000 | ||
| 15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 7:0 | SELECT | Selects one or more resources from the wanted group. One bit is provided per resource from the group | RW | 0x00 | ||
| Address Offset | 0x0000 020C | ||
| Physical Address | 0xE004 120C | Instance | 0xE004 120C |
| Description | The TRCRSCTLR controls the trace resources | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:22 | RESERVED22 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||
| 21 | PAIRINV | Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors | RW | 0 | ||
| 20 | INV | Inverts the selected resources | RW | 0 | ||
| 19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 18:16 | GROUP | Selects a group of resource | RW | 0b000 | ||
| 15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 7:0 | SELECT | Selects one or more resources from the wanted group. One bit is provided per resource from the group | RW | 0x00 | ||
| Address Offset | 0x0000 02A0 | ||
| Physical Address | 0xE004 12A0 | Instance | 0xE004 12A0 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02A4 | ||
| Physical Address | 0xE004 12A4 | Instance | 0xE004 12A4 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02A8 | ||
| Physical Address | 0xE004 12A8 | Instance | 0xE004 12A8 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02AC | ||
| Physical Address | 0xE004 12AC | Instance | 0xE004 12AC |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02B0 | ||
| Physical Address | 0xE004 12B0 | Instance | 0xE004 12B0 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02B4 | ||
| Physical Address | 0xE004 12B4 | Instance | 0xE004 12B4 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02B8 | ||
| Physical Address | 0xE004 12B8 | Instance | 0xE004 12B8 |
| Description | Controls the corresponding single-shot comparator resource | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | STATUS | Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched | RW | 0 | ||
| 30:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 3 | PC | PE comparator input support. Indicates if the trace unit supports Single-shot PE comparator inputs. This field is read-only | RW | 0 | ||
| 2 | DV | Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons. This field is read-only: | RW | 0 | ||
| 1 | DA | Data address comparator support bit. Indicates if the trace unit supports data address comparisons. This field is read-only: | RW | 0 | ||
| 0 | INST | Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons. This field is read-only: | RW | 0 | ||
| Address Offset | 0x0000 02C0 | ||
| Physical Address | 0xE004 12C0 | Instance | 0xE004 12C0 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02C4 | ||
| Physical Address | 0xE004 12C4 | Instance | 0xE004 12C4 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02C8 | ||
| Physical Address | 0xE004 12C8 | Instance | 0xE004 12C8 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02CC | ||
| Physical Address | 0xE004 12CC | Instance | 0xE004 12CC |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02D0 | ||
| Physical Address | 0xE004 12D0 | Instance | 0xE004 12D0 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02D4 | ||
| Physical Address | 0xE004 12D4 | Instance | 0xE004 12D4 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 02D8 | ||
| Physical Address | 0xE004 12D8 | Instance | 0xE004 12D8 |
| Description | Selects the PE comparator inputs for Single-shot control | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | PC1 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| 0 | PC0 | Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control | RW | 0 | ||
| Address Offset | 0x0000 0310 | ||
| Physical Address | 0xE004 1310 | Instance | 0xE004 1310 |
| Description | Requests the system to provide power to the trace unit | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | PU | Powerup request bit: | RW | 0 | ||
| 2:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| Address Offset | 0x0000 0314 | ||
| Physical Address | 0xE004 1314 | Instance | 0xE004 1314 |
| Description | Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||
| 5 | OSLK | OS Lock status bit: | RO | 0 | ||
| 4:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 1 | STICKYPD | Sticky powerdown status bit. Indicates whether the trace register state is valid: | RO | 0 | ||
| 0 | POWER | Power status bit: | RO | 0 | ||
| Address Offset | 0x0000 0EE4 | ||
| Physical Address | 0xE004 1EE4 | Instance | 0xE004 1EE4 |
| Description | Trace Intergration ATB Identification Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||
| 6:0 | ID | Trace ID | RW | 0b000 0000 | ||
| Address Offset | 0x0000 0EF4 | ||
| Physical Address | 0xE004 1EF4 | Instance | 0xE004 1EF4 |
| Description | Trace Integration Instruction ATB In Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | AFVALIDM | Integration Mode instruction AFVALIDM in | RW | 0 | ||
| 0 | ATREADYM | Integration Mode instruction ATREADYM in | RW | 0 | ||
| Address Offset | 0x0000 0EFC | ||
| Physical Address | 0xE004 1EFC | Instance | 0xE004 1EFC |
| Description | Trace Integration Instruction ATB Out Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | AFREADY | Integration Mode instruction AFREADY out | RW | 0 | ||
| 0 | ATVALID | Integration Mode instruction ATVALID out | RW | 0 | ||
| Address Offset | 0x0000 0FA0 | ||
| Physical Address | 0xE004 1FA0 | Instance | 0xE004 1FA0 |
| Description | Claim Tag Set Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | SET3 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 2 | SET2 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 1 | SET1 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 0 | SET0 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| Address Offset | 0x0000 0FA4 | ||
| Physical Address | 0xE004 1FA4 | Instance | 0xE004 1FA4 |
| Description | Claim Tag Clear Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 3 | CLR3 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 2 | CLR2 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 1 | CLR1 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| 0 | CLR0 | When a write to one of these bits occurs, with the value: | RW | 0 | ||
| Address Offset | 0x0000 0FB8 | ||
| Physical Address | 0xE004 1FB8 | Instance | 0xE004 1FB8 |
| Description | Returns the level of tracing that the trace unit can support | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:6 | SNID | Indicates whether the system enables the trace unit to support Secure non-invasive debug: | RO | 0b00 | ||
| 5:4 | SID | Indicates whether the trace unit supports Secure invasive debug: | RO | 0b00 | ||
| 3:2 | NSNID | Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: | RO | 0b00 | ||
| 1:0 | NSID | Indicates whether the trace unit supports Non-secure invasive debug: | RO | 0b00 | ||
| Address Offset | 0x0000 0FBC | ||
| Physical Address | 0xE004 1FBC | Instance | 0xE004 1FBC |
| Description | TRCDEVARCH | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:21 | ARCHITECT | reads as 0b01000111011 | RO | 0b000 0000 0000 | ||
| 20 | PRESENT | reads as 0b1 | RO | 0 | ||
| 19:16 | REVISION | reads as 0b0000 | RO | 0x0 | ||
| 15:0 | ARCHID | reads as 0b0100101000010011 | RO | 0x0000 | ||
| Address Offset | 0x0000 0FC8 | ||
| Physical Address | 0xE004 1FC8 | Instance | 0xE004 1FC8 |
| Description | TRCDEVID | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FCC | ||
| Physical Address | 0xE004 1FCC | Instance | 0xE004 1FCC |
| Description | TRCDEVTYPE | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SUB | reads as 0b0001 | RO | 0x0 | ||
| 3:0 | MAJOR | reads as 0b0011 | RO | 0x0 | ||
| Address Offset | 0x0000 0FD0 | ||
| Physical Address | 0xE004 1FD0 | Instance | 0xE004 1FD0 |
| Description | TRCPIDR4 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SIZE | reads as `ImpDef | RO | 0x0 | ||
| 3:0 | DES_2 | reads as `ImpDef | RO | 0x0 | ||
| Address Offset | 0x0000 0FD4 | ||
| Physical Address | 0xE004 1FD4 | Instance | 0xE004 1FD4 |
| Description | TRCPIDR5 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FD8 | ||
| Physical Address | 0xE004 1FD8 | Instance | 0xE004 1FD8 |
| Description | TRCPIDR6 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FDC | ||
| Physical Address | 0xE004 1FDC | Instance | 0xE004 1FDC |
| Description | TRCPIDR7 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FE0 | ||
| Physical Address | 0xE004 1FE0 | Instance | 0xE004 1FE0 |
| Description | TRCPIDR0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PART_0 | reads as `ImpDef | RO | 0x00 | ||
| Address Offset | 0x0000 0FE4 | ||
| Physical Address | 0xE004 1FE4 | Instance | 0xE004 1FE4 |
| Description | TRCPIDR1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | DES_0 | reads as `ImpDef | RO | 0x0 | ||
| 3:0 | PART_0 | reads as `ImpDef | RO | 0x0 | ||
| Address Offset | 0x0000 0FE8 | ||
| Physical Address | 0xE004 1FE8 | Instance | 0xE004 1FE8 |
| Description | TRCPIDR2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVISION | reads as `ImpDef | RO | 0x0 | ||
| 3 | JEDEC | reads as 0b1 | RO | 0 | ||
| 2:0 | DES_0 | reads as `ImpDef | RO | 0b000 | ||
| Address Offset | 0x0000 0FEC | ||
| Physical Address | 0xE004 1FEC | Instance | 0xE004 1FEC |
| Description | TRCPIDR3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVAND | reads as `ImpDef | RO | 0x0 | ||
| 3:0 | CMOD | reads as `ImpDef | RO | 0x0 | ||
| Address Offset | 0x0000 0FF0 | ||
| Physical Address | 0xE004 1FF0 | Instance | 0xE004 1FF0 |
| Description | TRCCIDR0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | reads as 0b00001101 | RO | 0x00 | ||
| Address Offset | 0x0000 0FF4 | ||
| Physical Address | 0xE004 1FF4 | Instance | 0xE004 1FF4 |
| Description | TRCCIDR1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | CLASS | reads as 0b1001 | RO | 0x0 | ||
| 3:0 | PRMBL_1 | reads as 0b0000 | RO | 0x0 | ||
| Address Offset | 0x0000 0FF8 | ||
| Physical Address | 0xE004 1FF8 | Instance | 0xE004 1FF8 |
| Description | TRCCIDR2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | reads as 0b00000101 | RO | 0x00 | ||
| Address Offset | 0x0000 0FFC | ||
| Physical Address | 0xE004 1FFC | Instance | 0xE004 1FFC |
| Description | TRCCIDR3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | reads as 0b10110001 | RO | 0x00 | ||
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