Instance: CPU_DWT
Component: CPU_DWT
Base address: 0xE0001000
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0xE000 1000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 1004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 1008 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0xE000 100C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 1010 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 1014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 1018 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0xE000 101C |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0020 |
0xE000 1020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 1028 |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0030 |
0xE000 1030 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0xE000 1038 |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0040 |
0xE000 1040 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0xE000 1048 |
|
|
RW |
32 |
0xXXXX XXXX |
0x0000 0050 |
0xE000 1050 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0xE000 1058 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FBC |
0xE000 1FBC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FCC |
0xE000 1FCC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD0 |
0xE000 1FD0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD4 |
0xE000 1FD4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FD8 |
0xE000 1FD8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FDC |
0xE000 1FDC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE0 |
0xE000 1FE0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE4 |
0xE000 1FE4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FE8 |
0xE000 1FE8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FEC |
0xE000 1FEC |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF0 |
0xE000 1FF0 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF4 |
0xE000 1FF4 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FF8 |
0xE000 1FF8 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0FFC |
0xE000 1FFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0xE000 1000 | Instance | 0xE000 1000 |
| Description | Provides configuration and status information for the DWT unit, and used to control features of the unit | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | NUMCOMP | Number of DWT comparators implemented | RO | 0x0 | ||
| 27 | NOTRCPKT | Indicates whether the implementation does not support trace | RO | 0 | ||
| 26 | NOEXTTRIG | Reserved, RAZ | RO | 0 | ||
| 25 | NOCYCCNT | Indicates whether the implementation does not include a cycle counter | RO | 0 | ||
| 24 | NOPRFCNT | Indicates whether the implementation does not include the profiling counters | RO | 0 | ||
| 23 | CYCDISS | Controls whether the cycle counter is disabled in Secure state | RO | 0 | ||
| 22 | CYCEVTENA | Enables Event Counter packet generation on POSTCNT underflow | RO | 0 | ||
| 21 | FOLDEVTENA | Enables DWT_FOLDCNT counter | RO | 0 | ||
| 20 | LSUEVTENA | Enables DWT_LSUCNT counter | RO | 0 | ||
| 19 | SLEEPEVTENA | Enable DWT_SLEEPCNT counter | RO | 0 | ||
| 18 | EXCEVTENA | Enables DWT_EXCCNT counter | RO | 0 | ||
| 17 | CPIEVTENA | Enables DWT_CPICNT counter | RO | 0 | ||
| 16 | EXTTRCENA | Enables generation of Exception Trace packets | RO | 0 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12 | PCSAMPLENA | Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation | RO | 0 | ||
| 11:10 | SYNCTAP | Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate | RO | 0b00 | ||
| 9 | CYCTAP | Selects the position of the POSTCNT tap on the CYCCNT counter | RO | 0 | ||
| 8:5 | POSTINIT | Initial value for the POSTCNT counter | RO | 0x0 | ||
| 4:1 | POSTPRESET | Reload value for the POSTCNT counter | RO | 0x0 | ||
| 0 | CYCCNTENA | Enables CYCCNT | RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0xE000 1004 | Instance | 0xE000 1004 |
| Description | Shows or sets the value of the processor cycle counter, CYCCNT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CYCCNT | Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero | RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0xE000 1008 | Instance | 0xE000 1008 |
| Description | CPI Count Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | CPICNT | Counts one on each cycle when all of the following are true: - DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed. - No load-store operation is in progress, see DWT_LSUCNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - The PE is not in a power saving mode, see DWT_SLEEPCNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. |
RW | 0x00 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0xE000 100C | Instance | 0xE000 100C |
| Description | Counts the total cycles spent in exception processing | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | EXCCNT | Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. |
RW | 0x00 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0xE000 1010 | Instance | 0xE000 1010 |
| Description | Sleep Count Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | SLEEPCNT | Counts one on each cycle when all of the following are true: - DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No load-store operation is in progress, see DWT_LSUCNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - The PE is in a power saving mode. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. |
RW | 0x00 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0xE000 1014 | Instance | 0xE000 1014 |
| Description | Increments on the additional cycles required to execute all load or store instructions | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | LSUCNT | Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. |
RW | 0x00 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0xE000 1018 | Instance | 0xE000 1018 |
| Description | Increments on the additional cycles required to execute all load or store instructions | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | FOLDCNT | Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one |
RW | 0x00 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0xE000 101C | Instance | 0xE000 101C |
| Description | Program Counter Sample Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | EIASAMPLE | The possible values of this field are: 0xFFFFFFFF One of the following is true: - The PE is halted in Debug state. - The Security Extension is implemented, the sampled instruction was executed in Secure state, and SecureNoninvasiveDebugAllowed() == FALSE. - NoninvasiveDebugAllowed() == FALSE. - DEMCR.TRCENA == 0. - The address of a recently-executed instruction is not available. Not 0xFFFFFFFF Instruction address of a recently executed instruction. Bit [0] of the sample instruction address is 0. |
RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0xE000 1020 | Instance | 0xE000 1020 |
| Description | Provides a reference value for use by watchpoint comparator 0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0xE000 1028 | Instance | 0xE000 1028 |
| Description | Controls the operation of watchpoint comparator 0 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:27 | ID | Identifies the capabilities for MATCH for comparator *n | RO | 0b0 0000 | ||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 24 | MATCHED | Set to 1 when the comparator matches | RO | 0 | ||
| 23:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 11:10 | DATAVSIZE | Defines the size of the object being watched for by Data Value and Data Address comparators | RW | 0b00 | ||
| 9:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 5:4 | ACTION | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH | RW | 0b00 | ||
| 3:0 | MATCH | Controls the type of match generated by this comparator | RW | 0x0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0xE000 1030 | Instance | 0xE000 1030 |
| Description | Provides a reference value for use by watchpoint comparator 1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0xE000 1038 | Instance | 0xE000 1038 |
| Description | Controls the operation of watchpoint comparator 1 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:27 | ID | Identifies the capabilities for MATCH for comparator *n | RO | 0b0 0000 | ||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 24 | MATCHED | Set to 1 when the comparator matches | RO | 0 | ||
| 23:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 11:10 | DATAVSIZE | Defines the size of the object being watched for by Data Value and Data Address comparators | RW | 0b00 | ||
| 9:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 5:4 | ACTION | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH | RW | 0b00 | ||
| 3:0 | MATCH | Controls the type of match generated by this comparator | RW | 0x0 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0xE000 1040 | Instance | 0xE000 1040 |
| Description | Provides a reference value for use by watchpoint comparator 2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| Address Offset | 0x0000 0048 | ||
| Physical Address | 0xE000 1048 | Instance | 0xE000 1048 |
| Description | Controls the operation of watchpoint comparator 2 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:27 | ID | Identifies the capabilities for MATCH for comparator *n | RO | 0b0 0000 | ||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 24 | MATCHED | Set to 1 when the comparator matches | RO | 0 | ||
| 23:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 11:10 | DATAVSIZE | Defines the size of the object being watched for by Data Value and Data Address comparators | RW | 0b00 | ||
| 9:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 5:4 | ACTION | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH | RW | 0b00 | ||
| 3:0 | MATCH | Controls the type of match generated by this comparator | RW | 0x0 | ||
| Address Offset | 0x0000 0050 | ||
| Physical Address | 0xE000 1050 | Instance | 0xE000 1050 |
| Description | Provides a reference value for use by watchpoint comparator 3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| Address Offset | 0x0000 0058 | ||
| Physical Address | 0xE000 1058 | Instance | 0xE000 1058 |
| Description | Controls the operation of watchpoint comparator 3 | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:27 | ID | Identifies the capabilities for MATCH for comparator *n | RO | 0b0 0000 | ||
| 26:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 24 | MATCHED | Set to 1 when the comparator matches | RO | 0 | ||
| 23:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 11:10 | DATAVSIZE | Defines the size of the object being watched for by Data Value and Data Address comparators | RW | 0b00 | ||
| 9:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 5:4 | ACTION | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH | RW | 0b00 | ||
| 3:0 | MATCH | Controls the type of match generated by this comparator | RW | 0x0 | ||
| Address Offset | 0x0000 0FBC | ||
| Physical Address | 0xE000 1FBC | Instance | 0xE000 1FBC |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:21 | ARCHITECT | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. | RO | 0b000 0000 0000 | ||
| 20 | PRESENT | Defines that the DEVARCH register is present | RO | 0 | ||
| 19:16 | REVISION | Defines the architecture revision of the component | RO | 0x0 | ||
| 15:12 | ARCHVER | Defines the architecture version of the component | RO | 0x0 | ||
| 11:0 | ARCHPART | Defines the architecture of the component | RO | 0x000 | ||
| Address Offset | 0x0000 0FCC | ||
| Physical Address | 0xE000 1FCC | Instance | 0xE000 1FCC |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SUB | Component sub-type | RO | 0x0 | ||
| 3:0 | MAJOR | Component major type | RO | 0x0 | ||
| Address Offset | 0x0000 0FD0 | ||
| Physical Address | 0xE000 1FD0 | Instance | 0xE000 1FD0 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | SIZE | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | DES_2 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FD4 | ||
| Physical Address | 0xE000 1FD4 | Instance | 0xE000 1FD4 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FD8 | ||
| Physical Address | 0xE000 1FD8 | Instance | 0xE000 1FD8 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FDC | ||
| Physical Address | 0xE000 1FDC | Instance | 0xE000 1FDC |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0FE0 | ||
| Physical Address | 0xE000 1FE0 | Instance | 0xE000 1FE0 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PART_0 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FE4 | ||
| Physical Address | 0xE000 1FE4 | Instance | 0xE000 1FE4 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | DES_0 | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | PART_1 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FE8 | ||
| Physical Address | 0xE000 1FE8 | Instance | 0xE000 1FE8 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVISION | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3 | JEDEC | See CoreSight Architecture Specification | RO | 0 | ||
| 2:0 | DES_1 | See CoreSight Architecture Specification | RO | 0b000 | ||
| Address Offset | 0x0000 0FEC | ||
| Physical Address | 0xE000 1FEC | Instance | 0xE000 1FEC |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | REVAND | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | CMOD | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FF0 | ||
| Physical Address | 0xE000 1FF0 | Instance | 0xE000 1FF0 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_0 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FF4 | ||
| Physical Address | 0xE000 1FF4 | Instance | 0xE000 1FF4 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:4 | CLASS | See CoreSight Architecture Specification | RO | 0x0 | ||
| 3:0 | PRMBL_1 | See CoreSight Architecture Specification | RO | 0x0 | ||
| Address Offset | 0x0000 0FF8 | ||
| Physical Address | 0xE000 1FF8 | Instance | 0xE000 1FF8 |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_2 | See CoreSight Architecture Specification | RO | 0x00 | ||
| Address Offset | 0x0000 0FFC | ||
| Physical Address | 0xE000 1FFC | Instance | 0xE000 1FFC |
| Description | Provides CoreSight discovery information for the DWT | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:0 | PRMBL_3 | See CoreSight Architecture Specification | RO | 0x00 | ||
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