CPU_CTI

Instance: CPU_CTI
Component: CPU_CTI
Base address: 0xE0042000


TOP:CPU_CTI Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTICONTROL

RW

32

0x0000 0000

0x0000 0000

0xE004 2000

CTIINTACK

RW

32

0x0000 0000

0x0000 0010

0xE004 2010

CTIAPPSET

RW

32

0x0000 0000

0x0000 0014

0xE004 2014

CTIAPPCLEAR

RW

32

0x0000 0000

0x0000 0018

0xE004 2018

CTIAPPPULSE

RW

32

0x0000 0000

0x0000 001C

0xE004 201C

CTIINEN0

RW

32

0x0000 0000

0x0000 0020

0xE004 2020

CTIINEN1

RW

32

0x0000 0000

0x0000 0024

0xE004 2024

CTIINEN2

RW

32

0x0000 0000

0x0000 0028

0xE004 2028

CTIINEN3

RW

32

0x0000 0000

0x0000 002C

0xE004 202C

CTIINEN4

RW

32

0x0000 0000

0x0000 0030

0xE004 2030

CTIINEN5

RW

32

0x0000 0000

0x0000 0034

0xE004 2034

CTIINEN6

RW

32

0x0000 0000

0x0000 0038

0xE004 2038

CTIINEN7

RW

32

0x0000 0000

0x0000 003C

0xE004 203C

CTIOUTEN0

RW

32

0x0000 0000

0x0000 00A0

0xE004 20A0

CTIOUTEN1

RW

32

0x0000 0000

0x0000 00A4

0xE004 20A4

CTIOUTEN2

RW

32

0x0000 0000

0x0000 00A8

0xE004 20A8

CTIOUTEN3

RW

32

0x0000 0000

0x0000 00AC

0xE004 20AC

CTIOUTEN4

RW

32

0x0000 0000

0x0000 00B0

0xE004 20B0

CTIOUTEN5

RW

32

0x0000 0000

0x0000 00B4

0xE004 20B4

CTIOUTEN6

RW

32

0x0000 0000

0x0000 00B8

0xE004 20B8

CTIOUTEN7

RW

32

0x0000 0000

0x0000 00BC

0xE004 20BC

CTITRIGINSTATUS

RW

32

0x0000 0000

0x0000 0130

0xE004 2130

CTITRIGOUTSTATUS

RW

32

0x0000 0000

0x0000 0134

0xE004 2134

CTICHINSTATUS

RW

32

0x0000 0000

0x0000 0138

0xE004 2138

CTIGATE

RW

32

0x0000 0000

0x0000 0140

0xE004 2140

ASICCTL

RW

32

0x0000 0000

0x0000 0144

0xE004 2144

ITCHOUT

RW

32

0x0000 0000

0x0000 0EE4

0xE004 2EE4

ITTRIGOUT

RW

32

0x0000 0000

0x0000 0EE8

0xE004 2EE8

ITCHIN

RW

32

0x0000 0000

0x0000 0EF4

0xE004 2EF4

ITCTRL

RW

32

0x0000 0000

0x0000 0F00

0xE004 2F00

DEVARCH

RW

32

0x0000 0000

0x0000 0FBC

0xE004 2FBC

DEVID

RW

32

0x0000 0000

0x0000 0FC8

0xE004 2FC8

DEVTYPE

RW

32

0x0000 0000

0x0000 0FCC

0xE004 2FCC

PIDR4

RW

32

0x0000 0000

0x0000 0FD0

0xE004 2FD0

PIDR5

RW

32

0x0000 0000

0x0000 0FD4

0xE004 2FD4

PIDR6

RW

32

0x0000 0000

0x0000 0FD8

0xE004 2FD8

PIDR7

RW

32

0x0000 0000

0x0000 0FDC

0xE004 2FDC

PIDR0

RW

32

0x0000 0000

0x0000 0FE0

0xE004 2FE0

PIDR1

RW

32

0x0000 0000

0x0000 0FE4

0xE004 2FE4

PIDR2

RW

32

0x0000 0000

0x0000 0FE8

0xE004 2FE8

PIDR3

RW

32

0x0000 0000

0x0000 0FEC

0xE004 2FEC

CIDR0

RW

32

0x0000 0000

0x0000 0FF0

0xE004 2FF0

CIDR1

RW

32

0x0000 0000

0x0000 0FF4

0xE004 2FF4

CIDR2

RW

32

0x0000 0000

0x0000 0FF8

0xE004 2FF8

CIDR3

RW

32

0x0000 0000

0x0000 0FFC

0xE004 2FFC

TOP:CPU_CTI Register Descriptions

TOP:CPU_CTI:CTICONTROL

Address Offset 0x0000 0000
Physical Address 0xE004 2000 Instance 0xE004 2000
Description CTI Control Register
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 GLBEN Enables or disables the CTI. RW 0

TOP:CPU_CTI:CTIINTACK

Address Offset 0x0000 0010
Physical Address 0xE004 2010 Instance 0xE004 2010
Description CTI Interrupt Acknowledge Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 INTACK Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared WO 0x00

TOP:CPU_CTI:CTIAPPSET

Address Offset 0x0000 0014
Physical Address 0xE004 2014 Instance 0xE004 2014
Description CTI Application Trigger Set Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 APPSET Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel. Reads as follows: 0 Application trigger is inactive. 1 Application trigger is active. Writes as follows: 0 No effect. 1 Generate channel event. RW 0x0

TOP:CPU_CTI:CTIAPPCLEAR

Address Offset 0x0000 0018
Physical Address 0xE004 2018 Instance 0xE004 2018
Description CTI Application Trigger Clear Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 APPCLEAR Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.On writes, for each bit: 0 Has no effect. 1 Clears the corresponding channel event.Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel. Reads as follows: 0 Application trigger is inactive. 1 Application trigger is active. Writes as follows: 0 No effect. 1 Generate channel event. RW 0x0

TOP:CPU_CTI:CTIAPPPULSE

Address Offset 0x0000 001C
Physical Address 0xE004 201C Instance 0xE004 201C
Description CTI Application Pulse Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 APPULSE Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. On writes, for each bit: 0 Has no effect. 1 Generate an event pulse on the corresponding channel. WO 0x0

TOP:CPU_CTI:CTIINEN0

Address Offset 0x0000 0020
Physical Address 0xE004 2020 Instance 0xE004 2020
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[0], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN1

Address Offset 0x0000 0024
Physical Address 0xE004 2024 Instance 0xE004 2024
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 1 events are ignored by the corresponding channel. 1 When an event is received on input trigger 1, ctitrigin[1], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN2

Address Offset 0x0000 0028
Physical Address 0xE004 2028 Instance 0xE004 2028
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 2 events are ignored by the corresponding channel. 1 When an event is received on input trigger 2, ctitrigin[2], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN3

Address Offset 0x0000 002C
Physical Address 0xE004 202C Instance 0xE004 202C
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 3 events are ignored by the corresponding channel. 1 When an event is received on input trigger 3, ctitrigin[3], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN4

Address Offset 0x0000 0030
Physical Address 0xE004 2030 Instance 0xE004 2030
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 4 events are ignored by the corresponding channel. 1 When an event is received on input trigger 4, ctitrigin[4], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN5

Address Offset 0x0000 0034
Physical Address 0xE004 2034 Instance 0xE004 2034
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 5 events are ignored by the corresponding channel. 1 When an event is received on input trigger 5, ctitrigin[5], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN6

Address Offset 0x0000 0038
Physical Address 0xE004 2038 Instance 0xE004 2038
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 6 events are ignored by the corresponding channel. 1 When an event is received on input trigger 6, ctitrigin[6], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIINEN7

Address Offset 0x0000 003C
Physical Address 0xE004 203C Instance 0xE004 203C
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 7 events are ignored by the corresponding channel. 1 When an event is received on input trigger 7, ctitrigin[7], generate an event on the channel corresponding to this bit. RW 0x0

TOP:CPU_CTI:CTIOUTEN0

Address Offset 0x0000 00A0
Physical Address 0xE004 20A0 Instance 0xE004 20A0
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 0, ctitrigout[0]. RW 0x0

TOP:CPU_CTI:CTIOUTEN1

Address Offset 0x0000 00A4
Physical Address 0xE004 20A4 Instance 0xE004 20A4
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 1. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 1, ctitrigout[1]. RW 0x0

TOP:CPU_CTI:CTIOUTEN2

Address Offset 0x0000 00A8
Physical Address 0xE004 20A8 Instance 0xE004 20A8
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 2. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 2, ctitrigout[2]. RW 0x0

TOP:CPU_CTI:CTIOUTEN3

Address Offset 0x0000 00AC
Physical Address 0xE004 20AC Instance 0xE004 20AC
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 3. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 3, ctitrigout[3]. RW 0x0

TOP:CPU_CTI:CTIOUTEN4

Address Offset 0x0000 00B0
Physical Address 0xE004 20B0 Instance 0xE004 20B0
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 4. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 4, ctitrigout[4]. RW 0x0

TOP:CPU_CTI:CTIOUTEN5

Address Offset 0x0000 00B4
Physical Address 0xE004 20B4 Instance 0xE004 20B4
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 5. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 5, ctitrigout[5]. RW 0x0

TOP:CPU_CTI:CTIOUTEN6

Address Offset 0x0000 00B8
Physical Address 0xE004 20B8 Instance 0xE004 20B8
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 6. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 6, ctitrigout[6]. RW 0x0

TOP:CPU_CTI:CTIOUTEN7

Address Offset 0x0000 00BC
Physical Address 0xE004 20BC Instance 0xE004 20BC
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 7. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 7, ctitrigout[7]. RW 0x0

TOP:CPU_CTI:CTITRIGINSTATUS

Address Offset 0x0000 0130
Physical Address 0xE004 2130 Instance 0xE004 2130
Description CTI Trigger to Channel Enable Registers
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 TRIGINSTATUS Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. 1 ctitrigin is active. 0 ctitrigin is inactive RO 0x00

TOP:CPU_CTI:CTITRIGOUTSTATUS

Address Offset 0x0000 0134
Physical Address 0xE004 2134 Instance 0xE004 2134
Description CTI Trigger In Status Register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 TRIGOUTSTATUS Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. 1 ctitrigout is active. 0 ctitrigout is inactive. RO 0x00

TOP:CPU_CTI:CTICHINSTATUS

Address Offset 0x0000 0138
Physical Address 0xE004 2138 Instance 0xE004 2138
Description CTI Channel In Status Register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 CTICHINSTATUS Shows the status of the ctichin inputs. There is one bit of the field for each channel input.Because the register provides a view of the raw ctichin inputs, the reset value is UNKNOWN. 0 ctichin is inactive. 1 ctichin is active. RO 0x0

TOP:CPU_CTI:CTIGATE

Address Offset 0x0000 0140
Physical Address 0xE004 2140 Instance 0xE004 2140
Description Enable CTI Channel Gate register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 CTIGATEEN3 Enable ctichout3. Set to 0 to disable channel propagation. RW 0
2 CTIGATEEN2 Enable ctichout2. Set to 0 to disable channel propagation. RW 0
1 CTIGATEEN1 Enable ctichout1. Set to 0 to disable channel propagation. RW 0
0 CTIGATEEN0 Enable ctichout0. Set to 0 to disable channel propagation. RW 0

TOP:CPU_CTI:ASICCTL

Address Offset 0x0000 0144
Physical Address 0xE004 2144 Instance 0xE004 2144
Description External Multiplexer Control register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 ASICCTL When external multiplexing is implemented for trigger signals, then the number of multiplexed signals on each trigger must be shown in the Device ID Register. This is done using a Verilog define EXTMUXNUM RW 0x00

TOP:CPU_CTI:ITCHOUT

Address Offset 0x0000 0EE4
Physical Address 0xE004 2EE4 Instance 0xE004 2EE4
Description Integration Test Channel Output register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 CTCHOUT Sets the value of the ctichout outputs WO 0x0

TOP:CPU_CTI:ITTRIGOUT

Address Offset 0x0000 0EE8
Physical Address 0xE004 2EE8 Instance 0xE004 2EE8
Description Integration Test Trigger Output register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 CTTRIGOUT Sets the value of the ctitrigout outputs WO 0x00

TOP:CPU_CTI:ITCHIN

Address Offset 0x0000 0EF4
Physical Address 0xE004 2EF4 Instance 0xE004 2EF4
Description Integration Test Channel Input register
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 CTCHIN Reads the value of the ctichin inputs RO 0x0

TOP:CPU_CTI:ITCTRL

Address Offset 0x0000 0F00
Physical Address 0xE004 2F00 Instance 0xE004 2F00
Description Integration Mode Control register
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 IME Integration Mode Enable. 0 Disable integration mode. 1 Enable integration mode RW 0

TOP:CPU_CTI:DEVARCH

Address Offset 0x0000 0FBC
Physical Address 0xE004 2FBC Instance 0xE004 2FBC
Description Device Architecture register
Type RW
Bits Field Name Description Type Reset
31:21 ARCHITECT Indicates the component architect: 0x23B ARM RO 0b000 0000 0000
20 PRESENT Indicates whether the DEVARCH register is present: 0x1 Present. RO 0
19:16 REVISION Indicates the architecture revision: 0x1 Revision 0. RO 0x0
15:0 ARCHID Indicates the component: 0x0A34 CoreSight GPR RO 0x0000

TOP:CPU_CTI:DEVID

Address Offset 0x0000 0FC8
Physical Address 0xE004 2FC8 Instance 0xE004 2FC8
Description Device Configuration register
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:16 NUMCH Number of ECT channels available RO 0x0
15:8 NUMTRIG Number of ECT triggers available RO 0x00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 EXTMUXNUM Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. RO 0b0 0000

TOP:CPU_CTI:DEVTYPE

Address Offset 0x0000 0FCC
Physical Address 0xE004 2FCC Instance 0xE004 2FCC
Description Device Type Identifier register
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 SUB Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. 0b0001 Indicates that this component is a cross-triggering component RO 0x0
3:0 MAJOR Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. 0b0100 Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. RO 0x0

TOP:CPU_CTI:PIDR4

Address Offset 0x0000 0FD0
Physical Address 0xE004 2FD0 Instance 0xE004 2FD0
Description CoreSight Periperal ID4
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 SIZE Always 0b0000. Indicates that the device only occupies 4KB of memory. RO 0x0
3:0 DES_2 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b0100 JEDEC continuation code. RO 0x0

TOP:CPU_CTI:PIDR5

Address Offset 0x0000 0FD4
Physical Address 0xE004 2FD4 Instance 0xE004 2FD4
Description CoreSight Periperal ID5
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:CPU_CTI:PIDR6

Address Offset 0x0000 0FD8
Physical Address 0xE004 2FD8 Instance 0xE004 2FD8
Description CoreSight Periperal ID6
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:CPU_CTI:PIDR7

Address Offset 0x0000 0FDC
Physical Address 0xE004 2FDC Instance 0xE004 2FDC
Description CoreSight Periperal ID7
Type RW
Bits Field Name Description Type Reset
31:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000 0000

TOP:CPU_CTI:PIDR0

Address Offset 0x0000 0FE0
Physical Address 0xE004 2FE0 Instance 0xE004 2FE0
Description CoreSight Periperal ID0
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PART_0 Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0x06 Indicates bits[7:0] of the part number of the component. RO 0x00

TOP:CPU_CTI:PIDR1

Address Offset 0x0000 0FE4
Physical Address 0xE004 2FE4 Instance 0xE004 2FE4
Description CoreSight Periperal ID1
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 DES_0 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. RO 0x0
3:0 PART_1 Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0b1001 Indicates bits[11:8] of the part number of the component. RO 0x0

TOP:CPU_CTI:PIDR2

Address Offset 0x0000 0FE8
Physical Address 0xE004 2FE8 Instance 0xE004 2FE8
Description CoreSight Periperal ID2
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 REVISION 0b0101 This device is at r1p0. RO 0x0
3 JEDEC Always 1. Indicates that the JEDEC-assigned designer ID is used RO 0
2:0 DES_1 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code RO 0b000

TOP:CPU_CTI:PIDR3

Address Offset 0x0000 0FEC
Physical Address 0xE004 2FEC Instance 0xE004 2FEC
Description CoreSight Periperal ID3
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 0b0000 Indicates that there are no errata fixes to this component. RO 0x0
3:0 CMOD Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0b0000 Indicates that the customer has not modified this component. RO 0x0

TOP:CPU_CTI:CIDR0

Address Offset 0x0000 0FF0
Physical Address 0xE004 2FF0 Instance 0xE004 2FF0
Description CoreSight Component ID0
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_0 Preamble[0]. Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. RO 0x00

TOP:CPU_CTI:CIDR1

Address Offset 0x0000 0FF4
Physical Address 0xE004 2FF4 Instance 0xE004 2FF4
Description CoreSight Component ID1
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:4 CLASS Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight component. RO 0x0
3:0 PRMBL_1 Preamble[1]. Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. RO 0x0

TOP:CPU_CTI:CIDR2

Address Offset 0x0000 0FF8
Physical Address 0xE004 2FF8 Instance 0xE004 2FF8
Description CoreSight Component ID2
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_2 Preamble[2]. Contains bits[23:16] of the component identification code. 0x05 Bits[23:16] of the identification code. RO 0x00

TOP:CPU_CTI:CIDR3

Address Offset 0x0000 0FFC
Physical Address 0xE004 2FFC Instance 0xE004 2FFC
Description CoreSight Component ID3
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 PRMBL_3 Preamble[3]. Contains bits[31:24] of the component identification code. 0xB1 Bits[31:24] of the identification code. RO 0x00


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