AUX_SCE

Instance: AUX_SCE
Component: AUX_SCE
Base address: 0x580E1000


AUX Sensor Control Engine (AUX_SCE) is a RISC-style microprocessor with separate fetch and execution cycles. It is optimized for low power and simple operations. AUX_SCE code and data segments are stored in AUX_RAM. AON_PMCTL:AUXSCECLK sets the operational frequency.

TOP:AUX_SCE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL

RW

32

0x0000 0000

0x0000 0000

0x580E 1000

FETCHSTAT

RO

32

0x0000 0000

0x0000 0004

0x580E 1004

CPUSTAT

RO

32

0x0000 0000

0x0000 0008

0x580E 1008

WUSTAT

RO

32

0x0000 0000

0x0000 000C

0x580E 100C

REG1_0

RO

32

0x0000 0000

0x0000 0010

0x580E 1010

REG3_2

RO

32

0x0000 0000

0x0000 0014

0x580E 1014

REG5_4

RO

32

0x0000 0000

0x0000 0018

0x580E 1018

REG7_6

RO

32

0x0000 0000

0x0000 001C

0x580E 101C

LOOPADDR

RO

32

0x0000 0000

0x0000 0020

0x580E 1020

LOOPCNT

RO

32

0x0000 0000

0x0000 0024

0x580E 1024

NONSECDDIACC0

RW

32

0x0000 0000

0x0000 0028

0x580E 1028

NONSECDDIACC1

RW

32

0x0000 0000

0x0000 002C

0x580E 102C

NONSECDDIACC2

RW

32

0x0000 0000

0x0000 0030

0x580E 1030

NONSECDDIACC3

RW

32

0x0000 0000

0x0000 0034

0x580E 1034

TOP:AUX_SCE Register Descriptions

TOP:AUX_SCE:CTL

Address Offset 0x0000 0000
Physical Address 0x580E 1000 Instance 0x580E 1000
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:24 FORCE_EV_LOW Internal. Only to be used through TI provided API. RW 0x00
23:16 FORCE_EV_HIGH Internal. Only to be used through TI provided API. RW 0x00
15:8 RESET_VECTOR Internal. Only to be used through TI provided API. RW 0x00
7 RESERVED7 Internal. Only to be used through TI provided API. RO 0
6 DBG_FREEZE_EN Internal. Only to be used through TI provided API. RW 0
5 FORCE_WU_LOW Internal. Only to be used through TI provided API. RW 0
4 FORCE_WU_HIGH Internal. Only to be used through TI provided API. RW 0
3 RESTART Internal. Only to be used through TI provided API. RW 0
2 SINGLE_STEP Internal. Only to be used through TI provided API. RW 0
1 SUSPEND Internal. Only to be used through TI provided API. RW 0
0 CLK_EN Internal. Only to be used through TI provided API. RW 0

TOP:AUX_SCE:FETCHSTAT

Address Offset 0x0000 0004
Physical Address 0x580E 1004 Instance 0x580E 1004
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 OPCODE Internal. Only to be used through TI provided API. RO 0x0000
15:0 PC Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:CPUSTAT

Address Offset 0x0000 0008
Physical Address 0x580E 1008 Instance 0x580E 1008
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Internal. Only to be used through TI provided API. RO 0x0 0000
11 BUS_ERROR Internal. Only to be used through TI provided API. RO 0
10 SLEEP Internal. Only to be used through TI provided API. RO 0
9 WEV Internal. Only to be used through TI provided API. RO 0
8 HALTED Internal. Only to be used through TI provided API. RO 0
7:4 RESERVED4 Internal. Only to be used through TI provided API. RO 0x0
3 V_FLAG Internal. Only to be used through TI provided API. RO 0
2 C_FLAG Internal. Only to be used through TI provided API. RO 0
1 N_FLAG Internal. Only to be used through TI provided API. RO 0
0 Z_FLAG Internal. Only to be used through TI provided API. RO 0

TOP:AUX_SCE:WUSTAT

Address Offset 0x0000 000C
Physical Address 0x580E 100C Instance 0x580E 100C
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:19 RESERVED20 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000
18:16 EXC_VECTOR Internal. Only to be used through TI provided API. RO 0b000
15:9 RESERVED9 Internal. Only to be used through TI provided API. RO 0b000 0000
8 WU_SIGNAL Internal. Only to be used through TI provided API. RO 0
7:0 EV_SIGNALS Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x1 AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API.
0x2 AUX_COMPA Internal. Only to be used through TI provided API.
0x4 AUX_COMPB Internal. Only to be used through TI provided API.
0x8 AUX_TDC_DONE Internal. Only to be used through TI provided API.
0x10 AUX_TIMER0_EV_OR_IDLE Internal. Only to be used through TI provided API.
0x20 AUX_TIMER1_EV_OR_IDLE Internal. Only to be used through TI provided API.
0x40 AUX_ADC_FIFO_NOT_EMPTY Internal. Only to be used through TI provided API.
0x80 SCEWEV_PROG Internal. Only to be used through TI provided API.
RO 0x00

TOP:AUX_SCE:REG1_0

Address Offset 0x0000 0010
Physical Address 0x580E 1010 Instance 0x580E 1010
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 REG1 Internal. Only to be used through TI provided API. RO 0x0000
15:0 REG0 Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:REG3_2

Address Offset 0x0000 0014
Physical Address 0x580E 1014 Instance 0x580E 1014
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 REG3 Internal. Only to be used through TI provided API. RO 0x0000
15:0 REG2 Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:REG5_4

Address Offset 0x0000 0018
Physical Address 0x580E 1018 Instance 0x580E 1018
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 REG5 Internal. Only to be used through TI provided API. RO 0x0000
15:0 REG4 Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:REG7_6

Address Offset 0x0000 001C
Physical Address 0x580E 101C Instance 0x580E 101C
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 REG7 Internal. Only to be used through TI provided API. RO 0x0000
15:0 REG6 Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:LOOPADDR

Address Offset 0x0000 0020
Physical Address 0x580E 1020 Instance 0x580E 1020
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:16 STOP Internal. Only to be used through TI provided API. RO 0x0000
15:0 START Internal. Only to be used through TI provided API. RO 0x0000

TOP:AUX_SCE:LOOPCNT

Address Offset 0x0000 0024
Physical Address 0x580E 1024 Instance 0x580E 1024
Description Internal. Only to be used through TI provided API.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Internal. Only to be used through TI provided API. RO 0x00 0000
7:0 ITER_LEFT Internal. Only to be used through TI provided API. RO 0x00

TOP:AUX_SCE:NONSECDDIACC0

Address Offset 0x0000 0028
Physical Address 0x580E 1028 Instance 0x580E 1028
Description Non-Secure DDI Access 0

When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.

If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.

Examples:

Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22 RD_EN Read Enable

0: AUX_SCE is not allowed to read DDI half-word given by ADDR.
1: AUX_SCE is allowed to read DDI half-word given by ADDR.		 RW 0
21:16 ADDR Address

AUX_SCE is allowed to update this DDI half-word using SET or CLR access.		 RW 0b00 0000
15:0 WR_MASK Mask

AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask.		 RW 0x0000

TOP:AUX_SCE:NONSECDDIACC1

Address Offset 0x0000 002C
Physical Address 0x580E 102C Instance 0x580E 102C
Description Non-Secure DDI Access 1

When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.

If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.

Examples:

Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22 RD_EN Read Enable

0: AUX_SCE is not allowed to read DDI half-word given by ADDR.
1: AUX_SCE is allowed to read DDI half-word given by ADDR.		 RW 0
21:16 ADDR Address

AUX_SCE is allowed to update this DDI half-word using SET or CLR access.		 RW 0b00 0000
15:0 WR_MASK Mask

AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask.		 RW 0x0000

TOP:AUX_SCE:NONSECDDIACC2

Address Offset 0x0000 0030
Physical Address 0x580E 1030 Instance 0x580E 1030
Description Non-Secure DDI Access 2

When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.

If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.

Examples:

Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22 RD_EN Read Enable

0: AUX_SCE is not allowed to read DDI half-word given by ADDR.
1: AUX_SCE is allowed to read DDI half-word given by ADDR.		 RW 0
21:16 ADDR Address

AUX_SCE is allowed to update this DDI half-word using SET or CLR access.		 RW 0b00 0000
15:0 WR_MASK Mask

AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask.		 RW 0x0000

TOP:AUX_SCE:NONSECDDIACC3

Address Offset 0x0000 0034
Physical Address 0x580E 1034 Instance 0x580E 1034
Description Non-Secure DDI Access 3

When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.

If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.

Examples:

Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22 RD_EN Read Enable

0: AUX_SCE is not allowed to read DDI half-word given by ADDR.
1: AUX_SCE is allowed to read DDI half-word given by ADDR.		 RW 0
21:16 ADDR Address

AUX_SCE is allowed to update this DDI half-word using SET or CLR access.		 RW 0b00 0000
15:0 WR_MASK Mask

AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask.		 RW 0x0000


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