Performs the necessary trim of the device which is not done in ROM boot code.
This function should only execute coming from ROM boot.
127 uint32_t ui32Fcfg1Revision;
128 uint32_t ui32AonSysResetctl;
132 ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
133 if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
134 ui32Fcfg1Revision = 0;
142 #if ( CCFG_BASE == CCFG_BASE_DEFAULT ) 145 NOROM_SetupSetCacheModeAccordingToCcfgSetting();
157 if( ! ( HWREG( AON_IOC_BASE + AON_IOC_O_IOCLATCH ) & AON_IOC_IOCLATCH_EN ))
170 else if( ! ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL ) & AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS ))
197 HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;
202 if ((( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
203 ( AON_PMCTL_RESETCTL_BOOT_DET_1_M | AON_PMCTL_RESETCTL_BOOT_DET_0_M )) >>
204 AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
206 ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
207 ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M |
208 AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ));
209 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M;
210 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl;
241 while ( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_CHANGING ) {
252 HWREG( ADI3_BASE + ADI_O_NONSECWR0) = (( 0x00 << ADI_NONSECWR0_DATA_S) & ADI_NONSECWR0_DATA_M ) |
253 ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR0_ADDR_S ) & ADI_NONSECWR0_ADDR_M) |
254 (( 0x0F << ADI_NONSECWR0_WR_MASK_S) & ADI_NONSECWR0_WR_MASK_M);
257 HWREG( ADI3_BASE + ADI_O_NONSECWR1) = (( 0x08 << ADI_NONSECWR1_DATA_S) & ADI_NONSECWR1_DATA_M ) |
258 ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR1_ADDR_S ) & ADI_NONSECWR1_ADDR_M) |
259 (( 0x0F << ADI_NONSECWR1_WR_MASK_S) & ADI_NONSECWR1_WR_MASK_M);
262 HWREG( ADI3_BASE + ADI_O_NONSECWR2) = (( 0x03 << ADI_NONSECWR2_DATA_S) & ADI_NONSECWR2_DATA_M ) |
263 ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR2_ADDR_S ) & ADI_NONSECWR2_ADDR_M) |
264 (( 0x0F << ADI_NONSECWR2_WR_MASK_S) & ADI_NONSECWR2_WR_MASK_M);
267 HWREG( ADI3_BASE + ADI_O_NONSECWR3) = (( 0x07 << ADI_NONSECWR3_DATA_S) & ADI_NONSECWR3_DATA_M ) |
268 ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR3_ADDR_S ) & ADI_NONSECWR3_ADDR_M) |
269 (( 0x0F << ADI_NONSECWR3_WR_MASK_S) & ADI_NONSECWR3_WR_MASK_M);
280 HWREG( AUX_SCE_BASE + AUX_SCE_O_NONSECDDIACC3) = AUX_SCE_NONSECDDIACC3_RD_EN |
281 (( ( DDI_0_OSC_O_CTL0 / 2 ) << AUX_SCE_NONSECDDIACC3_ADDR_S ) & AUX_SCE_NONSECDDIACC3_ADDR_M ) |
282 (( DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M ) & AUX_SCE_NONSECDDIACC3_WR_MASK_M );
290 HWREG( AUX_SCE_BASE + AUX_SCE_O_NONSECDDIACC2) = AUX_SCE_NONSECDDIACC2_RD_EN |
291 (( ( DDI_0_OSC_O_STAT2 / 2 ) << AUX_SCE_NONSECDDIACC2_ADDR_S ) & AUX_SCE_NONSECDDIACC2_ADDR_M);
302 HWREG( AUX_SCE_BASE + AUX_SCE_O_NONSECDDIACC1) = AUX_SCE_NONSECDDIACC1_RD_EN |
303 ((( ( DDI_0_OSC_O_ATESTCTL + 2 ) / 2 ) << AUX_SCE_NONSECDDIACC1_ADDR_S ) & AUX_SCE_NONSECDDIACC1_ADDR_M) |
304 (( DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M >> 16 ) & AUX_SCE_NONSECDDIACC1_WR_MASK_M);
307 HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M;
#define AON_RTC_CH1
Definition: aon_rtc.h:93
void IntPendClear(uint32_t ui32Interrupt)
Unpends an interrupt.
Definition: interrupt.c:441
void ThisLibraryIsFor_CC13x4_CC26x4_HaltIfViolated(void)
Verifies that current chip is CC13x4 or CC26x4 and never returns if violated.
Definition: chipinfo.c:196
#define AON_RTC_CH2
Definition: aon_rtc.h:94
#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF
Definition: ccfgread.h:116
static void AONRTCCombinedEventConfig(uint32_t ui32Channels)
Configure the source of the combined event.
Definition: aon_rtc.h:335
static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(void)
Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET)...
Definition: setup.c:319
static void AONRTCReset(void)
Reset the RTC.
Definition: aon_rtc.h:209
#define AON_RTC_CH0
Definition: aon_rtc.h:92
static uint32_t CCFGRead_SCLK_LF_OPTION(void)
Read SCLK_LF_OPTION from CCFG.
Definition: ccfgread.h:132
void SetupSetAonRtcSubSecInc(uint32_t subSecInc)
Doing the tricky stuff needed to enter new RTCSUBSECINC value.
Definition: setup_rom.c:926
static void TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).
Definition: setup.c:335
static void AONRTCEnable(void)
Enable the RTC.
Definition: aon_rtc.h:172
void SetupSetCacheModeAccordingToCcfgSetting(void)
Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)
Definition: setup_rom.c:881
#define SUBSECINC_31250_HZ
Definition: setup.c:103
static void TrimAfterColdReset(void)
Trims to be applied when coming from PIN_RESET.
Definition: setup.c:435