setup.c File Reference

#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_adi.h"
#include "../inc/hw_adi_2_refsys.h"
#include "../inc/hw_adi_3_refsys.h"
#include "../inc/hw_adi_4_aux.h"
#include "../inc/hw_aon_ioc.h"
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_aon_rtc.h"
#include "../inc/hw_ddi_0_osc.h"
#include "../inc/hw_ddi.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_flash.h"
#include "../inc/hw_prcm.h"
#include "../inc/hw_vims.h"
#include "aon_rtc.h"
#include "interrupt.h"
#include "aux_sysif.h"
#include "chipinfo.h"
#include "osc.h"
#include "setup.h"
#include "setup_rom.h"
#include "ccfgread.h"

Macros
#define	ADI_4_AUX_O_LPMBIAS   0x0000000E
#define	ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M   0x0000003F
#define	ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S   0
#define	ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M   0x00000038
#define	ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S   3
#define	CPU_DELAY_MICRO_SECONDS(x)   CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
#define	SUBSECINC_31250_HZ   0x8637BD
#define	SUBSECINC_32768_HZ   0x800000

Functions
static void	TrimAfterColdReset (void)
	Trims to be applied when coming from PIN_RESET. More...
static void	TrimAfterColdResetWakeupFromShutDown (uint32_t ui32Fcfg1Revision)
	Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET). More...
static void	TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown (void)
	Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET). More...
void	SetupTrimDevice (void)
	Performs the necessary trim of the device which is not done in ROM boot code. More...

Macro Definition Documentation

ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M

#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M   0x00000038

Referenced by TrimAfterColdResetWakeupFromShutDown().

ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S

#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S   3

Referenced by TrimAfterColdResetWakeupFromShutDown().

ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M   0x0000003F

Referenced by TrimAfterColdResetWakeupFromShutDown().

ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S   0

Referenced by TrimAfterColdResetWakeupFromShutDown().

ADI_4_AUX_O_LPMBIAS

#define ADI_4_AUX_O_LPMBIAS   0x0000000E

Referenced by TrimAfterColdResetWakeupFromShutDown().

CPU_DELAY_MICRO_SECONDS

#define CPU_DELAY_MICRO_SECONDS

(

x

)

CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )

SUBSECINC_31250_HZ

#define SUBSECINC_31250_HZ   0x8637BD

Referenced by SetupTrimDevice().

SUBSECINC_32768_HZ

#define SUBSECINC_32768_HZ   0x800000

Function Documentation

TrimAfterColdReset()

static void TrimAfterColdReset ( void  )

static

Trims to be applied when coming from PIN_RESET.

Returns

None

Referenced by SetupTrimDevice().

{
    // Currently no specific trim for Cold Reset
}

TrimAfterColdResetWakeupFromShutDown()

static void TrimAfterColdResetWakeupFromShutDown ( uint32_t  ui32Fcfg1Revision )

static

Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).

Parameters

ui32Fcfg1Revision

Returns

None

Referenced by SetupTrimDevice().

{
    uint32_t   ccfg_ModeConfReg  ;

    // Check in CCFG for alternative DCDC setting
    if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
        // ADI_3_REFSYS:DCDCCTL5[3]  (=DITHER_EN) = CCFG_MODE_CONF_1[19]   (=ALT_DCDC_DITHER_EN)
        // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK    ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK    )
        // Using a single 4-bit masked write since layout is equal for both source and destination
        HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
            ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
    }

    {
        // Check if the RCOSC_HF trims have to be reloaded - this is a workaround needed on one specific production lot
        uint32_t fcfg1MiscTrimReg = HWREG( FCFG1_BASE + FCFG1_O_MISC_TRIM );
        if (( fcfg1MiscTrimReg & 0x80000000 ) == 0 ) {
            // Reload the RCOSCHF_CTRIM with the CTRIM found in the FCFG1 shadow register.
            HWREGB( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL + 1 ) =
               ((( HWREG( FCFG1_BASE + FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM ) & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M ) >> FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S ) ^ 0xC0 );
            // Reload the RCOSCHF_FINE_RESISTOR trim with the MISC_TRIM[30:29] (Mask bits in [7:6]=0xC0, Data in [3:2](0xC) (shift(29-2))
            HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ATESTCTL * 2 ) + 2 ) = ( 0xC0 | (( fcfg1MiscTrimReg >> 27 ) & 0xC ));
            // Set HFCTRIMFRACT_EN
            HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL1 ) = DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN ;
        }
    }

    // Force DCDC to use RCOSC before starting up XOSC.
    // Clock loss detector does not use XOSC until SCLK_HF actually switches
    // and thus DCDC is not protected from clock loss on XOSC in that time frame.
    // The force must be released when the switch to XOSC has happened. This is done
    // in OSCHfSourceSwitch().
    HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
    // Dummy read to ensure that the write has propagated
    HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);

    // read the MODE_CONF register in CCFG
    ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );

    // First part of trim done after cold reset and wakeup from shutdown:
    // -Adjust the VDDR_TRIM_SLEEP value.
    // -Configure DCDC.
    SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );

    // Addition to the CC1352 boost mode for HWREV >= 2.0
    // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
    if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD  ) == 0 ) &&
        (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 )    )
    {
        // OR in VDDR_BOOST_COMP_BOOST and maintain the other register fields.
        // On CC13X2, CC26X2, CC13X1 and CC26X1 devices, there are no other
        // fields in this register. But on CC26X4 and CC13X4 devices, there is
        // an additional trim field that must not be overwritten.
        HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) |= ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ;
    }

    // Second part of trim done after cold reset and wakeup from shutdown:
    // -Configure XOSC.
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
    SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
#else
    NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
#endif

    {
        uint32_t  trimReg        ;
        uint32_t  ui32TrimValue  ;

        //--- Propagate the LPM_BIAS trim ---
        trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF );
        ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >>
                                     FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
        HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) &
                                                                            ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ;
        // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration
        if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) {
            HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
        } else {
            HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
        }
        // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration
        {
            uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S );
            HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
                (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8         ) |       // Set mask (bits to be written) in [15:8]
                 ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S )   );    // Set value (in correct bit pos) in [7:0]
        }
    }

    // Third part of trim done after cold reset and wakeup from shutdown:
    // -Configure HPOSC.
    // -Setup the LF clock.
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
    SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
#else
    NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
#endif

    // Set AUX into power down active mode
    AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA );

    // Disable EFUSE clock
    HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
}

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TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()

static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown ( void  )

static

Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET).

Returns

None

Referenced by SetupTrimDevice().

{
    // Currently no specific trim for Powerdown
}