CC26xx Driver Library
Macros | Typedefs | Functions | Variables
flash.c File Reference
#include "../inc/hw_types.h"
#include "../inc/hw_ccfg.h"
#include "flash.h"
#include "rom.h"
#include "chipinfo.h"

Macros

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG
 
#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0
 
#define CCFG_SIZE_SECURITY   0x00000014
 
#define CCFG_SIZE_SECT_PROT   0x00000004
 

Typedefs

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)
 
typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)
 

Functions

static void SetReadMode (void)
 
void FlashPowerModeSet (uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)
 Set power mode. More...
 
uint32_t FlashPowerModeGet (void)
 Get current configured power mode. More...
 
void FlashProtectionSet (uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)
 Set sector protection. More...
 
uint32_t FlashProtectionGet (uint32_t ui32SectorAddress)
 Get sector protection. More...
 
uint32_t FlashProtectionSave (uint32_t ui32SectorAddress)
 Save sector protection to make it permanent. More...
 
uint32_t FlashSectorErase (uint32_t ui32SectorAddress)
 Erase a flash sector. More...
 
uint32_t FlashProgram (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 Programs unprotected flash sectors in the main bank. More...
 
bool FlashEfuseReadRow (uint32_t *pui32EfuseData, uint32_t ui32RowAddress)
 Reads efuse data from specified row. More...
 
void FlashDisableSectorsForWrite (void)
 Disables all sectors for erase and programming on the active bank. More...
 
uint32_t MemBusWrkAroundHapiProgramFlash (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 
uint32_t MemBusWrkAroundHapiEraseSector (uint32_t ui32Address)
 

Variables

const uint8_t g_pui8CcfgDefaultSec []
 

Macro Definition Documentation

§ CCFG_OFFSET_SECT_PROT

#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0

Referenced by FlashProtectionSave().

§ CCFG_OFFSET_SECURITY

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG

§ CCFG_SIZE_SECT_PROT

#define CCFG_SIZE_SECT_PROT   0x00000004

Referenced by FlashProtectionSave().

§ CCFG_SIZE_SECURITY

#define CCFG_SIZE_SECURITY   0x00000014

Typedef Documentation

§ FlashPrgPointer_t

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)

§ FlashSectorErasePointer_t

typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)

Function Documentation

§ MemBusWrkAroundHapiEraseSector()

uint32_t MemBusWrkAroundHapiEraseSector ( uint32_t  ui32Address)
648 {
649  uint32_t ui32ErrorReturn;
650 
651  FlashSectorErasePointer_t FuncPointer;
652  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4));
653 
654  // Call ROM function
655  FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr);
656  ui32ErrorReturn = FuncPointer(ui32Address);
657 
658  // Enable standby in flash bank since ROM function might have disabled it
659  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
660 
661  // Return status of operation.
662  return(ui32ErrorReturn);
663 }
FlashSectorErasePointer_t
uint32_t(* FlashSectorErasePointer_t)(uint32_t)
Definition: flash.c:97
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:104

§ MemBusWrkAroundHapiProgramFlash()

uint32_t MemBusWrkAroundHapiProgramFlash ( uint8_t *  pui8DataBuffer,
uint32_t  ui32Address,
uint32_t  ui32Count 
)
625 {
626  uint32_t ui32ErrorReturn;
627  FlashPrgPointer_t FuncPointer;
628  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4));
629 
630  // Call ROM function
631  FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr);
632  ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
633 
634  // Enable standby in flash bank since ROM function might have disabled it
635  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
636 
637  // Return status of operation.
638  return(ui32ErrorReturn);
639 }
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:104
FlashPrgPointer_t
uint32_t(* FlashPrgPointer_t)(uint8_t *, uint32_t, uint32_t)
Definition: flash.c:95

§ SetReadMode()

static void SetReadMode ( void  )
static

Referenced by FlashDisableSectorsForWrite().

476 {
477  uint32_t ui32TrimValue;
478  uint32_t ui32Value;
479 
480  // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
481  // VIN_AT_X and VIN_BY_PASS for read mode
482  if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
483  AON_PMCTL_PWRCTL_EXT_REG_MODE)
484  {
485  // Select trim values for external regulator mode:
486  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
487  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
488  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
489  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
490 
491  ui32TrimValue =
492  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
493 
494  ui32Value = ((ui32TrimValue &
495  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
496  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
497  FLASH_CFG_STANDBY_MODE_SEL_S;
498 
499  ui32Value |= ((ui32TrimValue &
500  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
501  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
502  FLASH_CFG_STANDBY_PW_SEL_S;
503 
504  // Configure DIS_STANDBY (OTP offset 0x308 bit 4).
505  // Configure DIS_IDLE (OTP offset 0x308 bit 3).
506  ui32Value |= ((ui32TrimValue &
507  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
508  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
509  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
510  FLASH_CFG_DIS_IDLE_S;
511 
512  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
513  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
514  FLASH_CFG_STANDBY_PW_SEL_M |
515  FLASH_CFG_DIS_STANDBY_M |
516  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
517 
518  // Check if sample and hold functionality is disabled.
519  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
520  {
521  // Wait for disabled sample and hold functionality to be stable.
522  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
523  {
524  }
525  }
526 
527  // Configure VIN_AT_X (OTP offset 0x308 bits 2:0)
528  ui32Value = ((ui32TrimValue &
529  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
530  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
531  FLASH_FSEQPMP_VIN_AT_X_S;
532 
533  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
534  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
535  // VIN_BY_PASS should be 1
536  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
537  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
538  {
539  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
540  }
541 
542  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
543  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
544  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
545  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
546  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
547  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
548  }
549  else
550  {
551  // Select trim values for internal regulator mode:
552  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
553  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
554  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
555  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
556 
557  ui32TrimValue =
558  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
559 
560  ui32Value = ((ui32TrimValue &
561  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
562  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
563  FLASH_CFG_STANDBY_MODE_SEL_S;
564 
565  ui32Value |= ((ui32TrimValue &
566  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
567  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
568  FLASH_CFG_STANDBY_PW_SEL_S;
569 
570  // Configure DIS_STANDBY (OTP offset 0x308 bit 12).
571  // Configure DIS_IDLE (OTP offset 0x308 bit 11).
572  ui32Value |= ((ui32TrimValue &
573  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
574  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
575  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
576  FLASH_CFG_DIS_IDLE_S;
577 
578  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
579  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
580  FLASH_CFG_STANDBY_PW_SEL_M |
581  FLASH_CFG_DIS_STANDBY_M |
582  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
583 
584  // Check if sample and hold functionality is disabled.
585  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
586  {
587  // Wait for disabled sample and hold functionality to be stable.
588  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
589  {
590  }
591  }
592 
593  // Configure VIN_AT_X (OTP offset 0x308 bits 10:8)
594  ui32Value = (((ui32TrimValue &
595  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
596  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
597  FLASH_FSEQPMP_VIN_AT_X_S);
598 
599  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
600  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
601  // VIN_BY_PASS should be 1
602  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
603  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
604  {
605  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
606  }
607 
608  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
609  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
610  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
611  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
612  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
613  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
614  }
615 }
FCFG1_OFFSET
#define FCFG1_OFFSET
Definition: flash.h:149

Variable Documentation

§ g_pui8CcfgDefaultSec

const uint8_t g_pui8CcfgDefaultSec[]
Initial value:
= {0xFF, 0xFF, 0xFF, 0xC5,
0xFF, 0xFF, 0xFF, 0xFF,
0xC5, 0xFF, 0xFF, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF
}