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#define CPU_ITM_O_STIM0 0x00000000 |
#define CPU_ITM_O_STIM1 0x00000004 |
#define CPU_ITM_O_STIM2 0x00000008 |
#define CPU_ITM_O_STIM3 0x0000000C |
#define CPU_ITM_O_STIM4 0x00000010 |
#define CPU_ITM_O_STIM5 0x00000014 |
#define CPU_ITM_O_STIM6 0x00000018 |
#define CPU_ITM_O_STIM7 0x0000001C |
#define CPU_ITM_O_STIM8 0x00000020 |
#define CPU_ITM_O_STIM9 0x00000024 |
#define CPU_ITM_O_STIM10 0x00000028 |
#define CPU_ITM_O_STIM11 0x0000002C |
#define CPU_ITM_O_STIM12 0x00000030 |
#define CPU_ITM_O_STIM13 0x00000034 |
#define CPU_ITM_O_STIM14 0x00000038 |
#define CPU_ITM_O_STIM15 0x0000003C |
#define CPU_ITM_O_STIM16 0x00000040 |
#define CPU_ITM_O_STIM17 0x00000044 |
#define CPU_ITM_O_STIM18 0x00000048 |
#define CPU_ITM_O_STIM19 0x0000004C |
#define CPU_ITM_O_STIM20 0x00000050 |
#define CPU_ITM_O_STIM21 0x00000054 |
#define CPU_ITM_O_STIM22 0x00000058 |
#define CPU_ITM_O_STIM23 0x0000005C |
#define CPU_ITM_O_STIM24 0x00000060 |
#define CPU_ITM_O_STIM25 0x00000064 |
#define CPU_ITM_O_STIM26 0x00000068 |
#define CPU_ITM_O_STIM27 0x0000006C |
#define CPU_ITM_O_STIM28 0x00000070 |
#define CPU_ITM_O_STIM29 0x00000074 |
#define CPU_ITM_O_STIM30 0x00000078 |
#define CPU_ITM_O_STIM31 0x0000007C |
#define CPU_ITM_O_TER 0x00000E00 |
#define CPU_ITM_O_TPR 0x00000E40 |
#define CPU_ITM_O_TCR 0x00000E80 |
#define CPU_ITM_O_LAR 0x00000FB0 |
#define CPU_ITM_O_LSR 0x00000FB4 |
#define CPU_ITM_STIM0_STIM0_W 32 |
#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF |
#define CPU_ITM_STIM0_STIM0_S 0 |
#define CPU_ITM_STIM1_STIM1_W 32 |
#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF |
#define CPU_ITM_STIM1_STIM1_S 0 |
#define CPU_ITM_STIM2_STIM2_W 32 |
#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF |
#define CPU_ITM_STIM2_STIM2_S 0 |
#define CPU_ITM_STIM3_STIM3_W 32 |
#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF |
#define CPU_ITM_STIM3_STIM3_S 0 |
#define CPU_ITM_STIM4_STIM4_W 32 |
#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF |
#define CPU_ITM_STIM4_STIM4_S 0 |
#define CPU_ITM_STIM5_STIM5_W 32 |
#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF |
#define CPU_ITM_STIM5_STIM5_S 0 |
#define CPU_ITM_STIM6_STIM6_W 32 |
#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF |
#define CPU_ITM_STIM6_STIM6_S 0 |
#define CPU_ITM_STIM7_STIM7_W 32 |
#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF |
#define CPU_ITM_STIM7_STIM7_S 0 |
#define CPU_ITM_STIM8_STIM8_W 32 |
#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF |
#define CPU_ITM_STIM8_STIM8_S 0 |
#define CPU_ITM_STIM9_STIM9_W 32 |
#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF |
#define CPU_ITM_STIM9_STIM9_S 0 |
#define CPU_ITM_STIM10_STIM10_W 32 |
#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF |
#define CPU_ITM_STIM10_STIM10_S 0 |
#define CPU_ITM_STIM11_STIM11_W 32 |
#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF |
#define CPU_ITM_STIM11_STIM11_S 0 |
#define CPU_ITM_STIM12_STIM12_W 32 |
#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF |
#define CPU_ITM_STIM12_STIM12_S 0 |
#define CPU_ITM_STIM13_STIM13_W 32 |
#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF |
#define CPU_ITM_STIM13_STIM13_S 0 |
#define CPU_ITM_STIM14_STIM14_W 32 |
#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF |
#define CPU_ITM_STIM14_STIM14_S 0 |
#define CPU_ITM_STIM15_STIM15_W 32 |
#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF |
#define CPU_ITM_STIM15_STIM15_S 0 |
#define CPU_ITM_STIM16_STIM16_W 32 |
#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF |
#define CPU_ITM_STIM16_STIM16_S 0 |
#define CPU_ITM_STIM17_STIM17_W 32 |
#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF |
#define CPU_ITM_STIM17_STIM17_S 0 |
#define CPU_ITM_STIM18_STIM18_W 32 |
#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF |
#define CPU_ITM_STIM18_STIM18_S 0 |
#define CPU_ITM_STIM19_STIM19_W 32 |
#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF |
#define CPU_ITM_STIM19_STIM19_S 0 |
#define CPU_ITM_STIM20_STIM20_W 32 |
#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF |
#define CPU_ITM_STIM20_STIM20_S 0 |
#define CPU_ITM_STIM21_STIM21_W 32 |
#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF |
#define CPU_ITM_STIM21_STIM21_S 0 |
#define CPU_ITM_STIM22_STIM22_W 32 |
#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF |
#define CPU_ITM_STIM22_STIM22_S 0 |
#define CPU_ITM_STIM23_STIM23_W 32 |
#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF |
#define CPU_ITM_STIM23_STIM23_S 0 |
#define CPU_ITM_STIM24_STIM24_W 32 |
#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF |
#define CPU_ITM_STIM24_STIM24_S 0 |
#define CPU_ITM_STIM25_STIM25_W 32 |
#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF |
#define CPU_ITM_STIM25_STIM25_S 0 |
#define CPU_ITM_STIM26_STIM26_W 32 |
#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF |
#define CPU_ITM_STIM26_STIM26_S 0 |
#define CPU_ITM_STIM27_STIM27_W 32 |
#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF |
#define CPU_ITM_STIM27_STIM27_S 0 |
#define CPU_ITM_STIM28_STIM28_W 32 |
#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF |
#define CPU_ITM_STIM28_STIM28_S 0 |
#define CPU_ITM_STIM29_STIM29_W 32 |
#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF |
#define CPU_ITM_STIM29_STIM29_S 0 |
#define CPU_ITM_STIM30_STIM30_W 32 |
#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF |
#define CPU_ITM_STIM30_STIM30_S 0 |
#define CPU_ITM_STIM31_STIM31_W 32 |
#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF |
#define CPU_ITM_STIM31_STIM31_S 0 |
#define CPU_ITM_TER_STIMENA31 0x80000000 |
#define CPU_ITM_TER_STIMENA31_BITN 31 |
#define CPU_ITM_TER_STIMENA31_M 0x80000000 |
#define CPU_ITM_TER_STIMENA31_S 31 |
#define CPU_ITM_TER_STIMENA30 0x40000000 |
#define CPU_ITM_TER_STIMENA30_BITN 30 |
#define CPU_ITM_TER_STIMENA30_M 0x40000000 |
#define CPU_ITM_TER_STIMENA30_S 30 |
#define CPU_ITM_TER_STIMENA29 0x20000000 |
#define CPU_ITM_TER_STIMENA29_BITN 29 |
#define CPU_ITM_TER_STIMENA29_M 0x20000000 |
#define CPU_ITM_TER_STIMENA29_S 29 |
#define CPU_ITM_TER_STIMENA28 0x10000000 |
#define CPU_ITM_TER_STIMENA28_BITN 28 |
#define CPU_ITM_TER_STIMENA28_M 0x10000000 |
#define CPU_ITM_TER_STIMENA28_S 28 |
#define CPU_ITM_TER_STIMENA27 0x08000000 |
#define CPU_ITM_TER_STIMENA27_BITN 27 |
#define CPU_ITM_TER_STIMENA27_M 0x08000000 |
#define CPU_ITM_TER_STIMENA27_S 27 |
#define CPU_ITM_TER_STIMENA26 0x04000000 |
#define CPU_ITM_TER_STIMENA26_BITN 26 |
#define CPU_ITM_TER_STIMENA26_M 0x04000000 |
#define CPU_ITM_TER_STIMENA26_S 26 |
#define CPU_ITM_TER_STIMENA25 0x02000000 |
#define CPU_ITM_TER_STIMENA25_BITN 25 |
#define CPU_ITM_TER_STIMENA25_M 0x02000000 |
#define CPU_ITM_TER_STIMENA25_S 25 |
#define CPU_ITM_TER_STIMENA24 0x01000000 |
#define CPU_ITM_TER_STIMENA24_BITN 24 |
#define CPU_ITM_TER_STIMENA24_M 0x01000000 |
#define CPU_ITM_TER_STIMENA24_S 24 |
#define CPU_ITM_TER_STIMENA23 0x00800000 |
#define CPU_ITM_TER_STIMENA23_BITN 23 |
#define CPU_ITM_TER_STIMENA23_M 0x00800000 |
#define CPU_ITM_TER_STIMENA23_S 23 |
#define CPU_ITM_TER_STIMENA22 0x00400000 |
#define CPU_ITM_TER_STIMENA22_BITN 22 |
#define CPU_ITM_TER_STIMENA22_M 0x00400000 |
#define CPU_ITM_TER_STIMENA22_S 22 |
#define CPU_ITM_TER_STIMENA21 0x00200000 |
#define CPU_ITM_TER_STIMENA21_BITN 21 |
#define CPU_ITM_TER_STIMENA21_M 0x00200000 |
#define CPU_ITM_TER_STIMENA21_S 21 |
#define CPU_ITM_TER_STIMENA20 0x00100000 |
#define CPU_ITM_TER_STIMENA20_BITN 20 |
#define CPU_ITM_TER_STIMENA20_M 0x00100000 |
#define CPU_ITM_TER_STIMENA20_S 20 |
#define CPU_ITM_TER_STIMENA19 0x00080000 |
#define CPU_ITM_TER_STIMENA19_BITN 19 |
#define CPU_ITM_TER_STIMENA19_M 0x00080000 |
#define CPU_ITM_TER_STIMENA19_S 19 |
#define CPU_ITM_TER_STIMENA18 0x00040000 |
#define CPU_ITM_TER_STIMENA18_BITN 18 |
#define CPU_ITM_TER_STIMENA18_M 0x00040000 |
#define CPU_ITM_TER_STIMENA18_S 18 |
#define CPU_ITM_TER_STIMENA17 0x00020000 |
#define CPU_ITM_TER_STIMENA17_BITN 17 |
#define CPU_ITM_TER_STIMENA17_M 0x00020000 |
#define CPU_ITM_TER_STIMENA17_S 17 |
#define CPU_ITM_TER_STIMENA16 0x00010000 |
#define CPU_ITM_TER_STIMENA16_BITN 16 |
#define CPU_ITM_TER_STIMENA16_M 0x00010000 |
#define CPU_ITM_TER_STIMENA16_S 16 |
#define CPU_ITM_TER_STIMENA15 0x00008000 |
#define CPU_ITM_TER_STIMENA15_BITN 15 |
#define CPU_ITM_TER_STIMENA15_M 0x00008000 |
#define CPU_ITM_TER_STIMENA15_S 15 |
#define CPU_ITM_TER_STIMENA14 0x00004000 |
#define CPU_ITM_TER_STIMENA14_BITN 14 |
#define CPU_ITM_TER_STIMENA14_M 0x00004000 |
#define CPU_ITM_TER_STIMENA14_S 14 |
#define CPU_ITM_TER_STIMENA13 0x00002000 |
#define CPU_ITM_TER_STIMENA13_BITN 13 |
#define CPU_ITM_TER_STIMENA13_M 0x00002000 |
#define CPU_ITM_TER_STIMENA13_S 13 |
#define CPU_ITM_TER_STIMENA12 0x00001000 |
#define CPU_ITM_TER_STIMENA12_BITN 12 |
#define CPU_ITM_TER_STIMENA12_M 0x00001000 |
#define CPU_ITM_TER_STIMENA12_S 12 |
#define CPU_ITM_TER_STIMENA11 0x00000800 |
#define CPU_ITM_TER_STIMENA11_BITN 11 |
#define CPU_ITM_TER_STIMENA11_M 0x00000800 |
#define CPU_ITM_TER_STIMENA11_S 11 |
#define CPU_ITM_TER_STIMENA10 0x00000400 |
#define CPU_ITM_TER_STIMENA10_BITN 10 |
#define CPU_ITM_TER_STIMENA10_M 0x00000400 |
#define CPU_ITM_TER_STIMENA10_S 10 |
#define CPU_ITM_TER_STIMENA9 0x00000200 |
#define CPU_ITM_TER_STIMENA9_BITN 9 |
#define CPU_ITM_TER_STIMENA9_M 0x00000200 |
#define CPU_ITM_TER_STIMENA9_S 9 |
#define CPU_ITM_TER_STIMENA8 0x00000100 |
#define CPU_ITM_TER_STIMENA8_BITN 8 |
#define CPU_ITM_TER_STIMENA8_M 0x00000100 |
#define CPU_ITM_TER_STIMENA8_S 8 |
#define CPU_ITM_TER_STIMENA7 0x00000080 |
#define CPU_ITM_TER_STIMENA7_BITN 7 |
#define CPU_ITM_TER_STIMENA7_M 0x00000080 |
#define CPU_ITM_TER_STIMENA7_S 7 |
#define CPU_ITM_TER_STIMENA6 0x00000040 |
#define CPU_ITM_TER_STIMENA6_BITN 6 |
#define CPU_ITM_TER_STIMENA6_M 0x00000040 |
#define CPU_ITM_TER_STIMENA6_S 6 |
#define CPU_ITM_TER_STIMENA5 0x00000020 |
#define CPU_ITM_TER_STIMENA5_BITN 5 |
#define CPU_ITM_TER_STIMENA5_M 0x00000020 |
#define CPU_ITM_TER_STIMENA5_S 5 |
#define CPU_ITM_TER_STIMENA4 0x00000010 |
#define CPU_ITM_TER_STIMENA4_BITN 4 |
#define CPU_ITM_TER_STIMENA4_M 0x00000010 |
#define CPU_ITM_TER_STIMENA4_S 4 |
#define CPU_ITM_TER_STIMENA3 0x00000008 |
#define CPU_ITM_TER_STIMENA3_BITN 3 |
#define CPU_ITM_TER_STIMENA3_M 0x00000008 |
#define CPU_ITM_TER_STIMENA3_S 3 |
#define CPU_ITM_TER_STIMENA2 0x00000004 |
#define CPU_ITM_TER_STIMENA2_BITN 2 |
#define CPU_ITM_TER_STIMENA2_M 0x00000004 |
#define CPU_ITM_TER_STIMENA2_S 2 |
#define CPU_ITM_TER_STIMENA1 0x00000002 |
#define CPU_ITM_TER_STIMENA1_BITN 1 |
#define CPU_ITM_TER_STIMENA1_M 0x00000002 |
#define CPU_ITM_TER_STIMENA1_S 1 |
#define CPU_ITM_TER_STIMENA0 0x00000001 |
#define CPU_ITM_TER_STIMENA0_BITN 0 |
#define CPU_ITM_TER_STIMENA0_M 0x00000001 |
#define CPU_ITM_TER_STIMENA0_S 0 |
#define CPU_ITM_TPR_PRIVMASK_W 4 |
#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F |
#define CPU_ITM_TPR_PRIVMASK_S 0 |
#define CPU_ITM_TCR_BUSY 0x00800000 |
#define CPU_ITM_TCR_BUSY_BITN 23 |
#define CPU_ITM_TCR_BUSY_M 0x00800000 |
#define CPU_ITM_TCR_BUSY_S 23 |
#define CPU_ITM_TCR_ATBID_W 7 |
#define CPU_ITM_TCR_ATBID_M 0x007F0000 |
#define CPU_ITM_TCR_ATBID_S 16 |
#define CPU_ITM_TCR_TSPRESCALE_W 2 |
#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 |
#define CPU_ITM_TCR_TSPRESCALE_S 8 |
#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 |
#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 |
#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 |
#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 |
#define CPU_ITM_TCR_SWOENA 0x00000010 |
#define CPU_ITM_TCR_SWOENA_BITN 4 |
#define CPU_ITM_TCR_SWOENA_M 0x00000010 |
#define CPU_ITM_TCR_SWOENA_S 4 |
#define CPU_ITM_TCR_DWTENA 0x00000008 |
#define CPU_ITM_TCR_DWTENA_BITN 3 |
#define CPU_ITM_TCR_DWTENA_M 0x00000008 |
#define CPU_ITM_TCR_DWTENA_S 3 |
#define CPU_ITM_TCR_SYNCENA 0x00000004 |
#define CPU_ITM_TCR_SYNCENA_BITN 2 |
#define CPU_ITM_TCR_SYNCENA_M 0x00000004 |
#define CPU_ITM_TCR_SYNCENA_S 2 |
#define CPU_ITM_TCR_TSENA 0x00000002 |
#define CPU_ITM_TCR_TSENA_BITN 1 |
#define CPU_ITM_TCR_TSENA_M 0x00000002 |
#define CPU_ITM_TCR_TSENA_S 1 |
#define CPU_ITM_TCR_ITMENA 0x00000001 |
#define CPU_ITM_TCR_ITMENA_BITN 0 |
#define CPU_ITM_TCR_ITMENA_M 0x00000001 |
#define CPU_ITM_TCR_ITMENA_S 0 |
#define CPU_ITM_LAR_LOCK_ACCESS_W 32 |
#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF |
#define CPU_ITM_LAR_LOCK_ACCESS_S 0 |
#define CPU_ITM_LSR_BYTEACC 0x00000004 |
#define CPU_ITM_LSR_BYTEACC_BITN 2 |
#define CPU_ITM_LSR_BYTEACC_M 0x00000004 |
#define CPU_ITM_LSR_BYTEACC_S 2 |
#define CPU_ITM_LSR_ACCESS 0x00000002 |
#define CPU_ITM_LSR_ACCESS_BITN 1 |
#define CPU_ITM_LSR_ACCESS_M 0x00000002 |
#define CPU_ITM_LSR_ACCESS_S 1 |
#define CPU_ITM_LSR_PRESENT 0x00000001 |
#define CPU_ITM_LSR_PRESENT_BITN 0 |
#define CPU_ITM_LSR_PRESENT_M 0x00000001 |
#define CPU_ITM_LSR_PRESENT_S 0 |