546 uint32_t ui32TrimValue;
551 if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
552 AON_PMCTL_PWRCTL_EXT_REG_MODE)
558 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
561 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
563 ui32Value = ((ui32TrimValue &
564 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
565 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
566 FLASH_CFG_STANDBY_MODE_SEL_S;
568 ui32Value |= ((ui32TrimValue &
569 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
570 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
571 FLASH_CFG_STANDBY_PW_SEL_S;
574 ui32Value |= ((ui32TrimValue &
575 FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M) >>
576 FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S) <<
577 FLASH_CFG_DIS_STANDBY_S;
579 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
580 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
581 FLASH_CFG_STANDBY_PW_SEL_M |
582 FLASH_CFG_DIS_STANDBY_M)) | ui32Value;
585 ui32Value = ((ui32TrimValue &
586 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
587 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
588 FLASH_FSEQPMP_VIN_AT_X_S;
593 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
594 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
596 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
599 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
600 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
601 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
602 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
603 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
604 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
612 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
615 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
617 ui32Value = ((ui32TrimValue &
618 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
619 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
620 FLASH_CFG_STANDBY_MODE_SEL_S;
622 ui32Value |= ((ui32TrimValue &
623 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
624 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
625 FLASH_CFG_STANDBY_PW_SEL_S;
628 ui32Value |= ((ui32TrimValue &
629 FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M) >>
630 FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S) <<
631 FLASH_CFG_DIS_STANDBY_S;
633 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
634 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
635 FLASH_CFG_STANDBY_PW_SEL_M |
636 FLASH_CFG_DIS_STANDBY_M)) | ui32Value;
639 ui32Value = (((ui32TrimValue &
640 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
641 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
642 FLASH_FSEQPMP_VIN_AT_X_S);
647 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
648 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
650 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
653 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
654 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
655 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
656 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
657 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
658 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
#define FCFG1_OFFSET
Definition: flash.h:149