Nested Vectored Interrupt Controller. More...

#include <ti/sysbios/family/arm/v8m/Hwi.h>

Data Fields
uint32_t	RES_00

uint32_t	ICTR

uint32_t	RES_08

uint32_t	RES_0C

uint32_t	STCSR

uint32_t	STRVR

uint32_t	STCVR

uint32_t	STCALIB

uint32_t	RES_20 [56]

uint32_t	ISER [16]

uint32_t	RES_140 [16]

uint32_t	ICER [16]

uint32_t	RES_1C0 [16]

uint32_t	ISPR [16]

uint32_t	RES_240 [16]

uint32_t	ICPR [16]

uint32_t	RES_2C0 [16]

uint32_t	IABR [16]

uint32_t	RES_340 [16]

uint32_t	ITNS [16]

uint32_t	RES_3C0 [16]

uint8_t	IPR [492]

uint32_t	RES_5F0 [453]

uint32_t	CPUIDBR

uint32_t	ICSR

uint32_t	VTOR

uint32_t	AIRCR

uint32_t	SCR

uint32_t	CCR

uint8_t	SHPR [12]

uint32_t	SHCSR

uint8_t	MMFSR

uint8_t	BFSR

uint16_t	UFSR

uint32_t	HFSR

uint32_t	DFSR

uint32_t	MMAR

uint32_t	BFAR

uint32_t	AFSR

uint32_t	PFR0

uint32_t	PFR1

uint32_t	DFR0

uint32_t	AFR0

uint32_t	MMFR0

uint32_t	MMFR1

uint32_t	MMFR2

uint32_t	MMFR3

uint32_t	ISAR0

uint32_t	ISAR1

uint32_t	ISAR2

uint32_t	ISAR3

uint32_t	ISAR4

uint32_t	ISAR5

uint32_t	CLIDR

uint32_t	CTR

uint32_t	CCSIDR

uint32_t	CSSELR

uint32_t	CPACR

uint32_t	NSACR

uint32_t	MPU_TYPE

uint32_t	MPU_CTRL

uint32_t	MPU_RNR

uint32_t	MPU_RBAR

uint32_t	MPU_RLAR

uint32_t	MPU_RBAR_An

uint32_t	MPU_RLAR_An

uint32_t	RES_DAC [5]

uint32_t	MPU_MAIR0

uint32_t	MPU_MAIR1

uint32_t	RES_DC8 [2]

uint32_t	SAU_CTRL

uint32_t	SAU_TYPE

uint32_t	SAU_RNR

uint32_t	SAU_RBAR

uint32_t	SAU_RLAR

uint32_t	SFSR

uint32_t	SFAR

uint32_t	RES_DEC

uint32_t	DHCSR

uint32_t	DCRSR

uint32_t	DCRDR

uint32_t	DEMCR

uint32_t	RES_E00

uint32_t	DAUTHCTRL

uint32_t	DSCSR

uint32_t	RES_E0C [61]

uint32_t	STI

uint32_t	RES_F04 [12]

uint32_t	FPCCR

uint32_t	FPCAR

uint32_t	FPDSCR

uint32_t	MVFR0

uint32_t	MVFR1

uint32_t	MVFR2

uint32_t	RES_F48

uint32_t	ICIALLU

uint32_t	RES_F54

uint32_t	ICIMVAU

uint32_t	DCIMVAC

uint32_t	DCISW

uint32_t	DCCMVAU

uint32_t	DCCMVAC

uint32_t	DCCSW

uint32_t	DCCIMVAC

uint32_t	DCCISW

uint32_t	BPIALL

uint32_t	RES_F7C [13]

uint32_t	DLAR

uint32_t	DLSR

uint32_t	DAUTHSTATUS

uint32_t	DDEVARCH

uint32_t	RES_FC0 [3]

uint32_t	DDEVTYPE

uint32_t	DPIDR4

uint32_t	DPIDR5

uint32_t	DPIDR6

uint32_t	DPIDR7

uint32_t	DPIDR0

uint32_t	DPIDR1

uint32_t	DPIDR2

uint32_t	DPIDR3

uint32_t	DCIDR0

uint32_t	DCIDR1

uint32_t	DCIDR2

uint32_t	DCIDR3

Detailed Description

Nested Vectored Interrupt Controller.

Field Documentation

§ RES_00

uint32_t Hwi_NVIC::RES_00

§ ICTR

uint32_t Hwi_NVIC::ICTR

0xE000E000 reserved

§ RES_08

uint32_t Hwi_NVIC::RES_08

0xE000E004 Interrupt Control Type

§ RES_0C

uint32_t Hwi_NVIC::RES_0C

0xE000E008 reserved

§ STCSR

uint32_t Hwi_NVIC::STCSR

0xE000E00C reserved

§ STRVR

uint32_t Hwi_NVIC::STRVR

0xE000E010 SysTick Control & Status Register

§ STCVR

uint32_t Hwi_NVIC::STCVR

0xE000E014 SysTick Reload Value Register

§ STCALIB

uint32_t Hwi_NVIC::STCALIB

0xE000E018 SysTick Current Value Register

§ RES_20

uint32_t Hwi_NVIC::RES_20[56]

0xE000E01C SysTick Calibration Value Register

§ ISER

uint32_t Hwi_NVIC::ISER[16]

0xE000E020-0xE000E0FC reserved

§ RES_140

uint32_t Hwi_NVIC::RES_140[16]

0xE000E100-0xE000E13C Interrupt Set Enable Registers

§ ICER

uint32_t Hwi_NVIC::ICER[16]

0xE000E140-0xE000E17C reserved

§ RES_1C0

uint32_t Hwi_NVIC::RES_1C0[16]

0xE000E180-0xE000E1BC Interrupt Clear Enable Registers

§ ISPR

uint32_t Hwi_NVIC::ISPR[16]

0xE000E1C0-0xE000E1FC reserved

§ RES_240

uint32_t Hwi_NVIC::RES_240[16]

0xE000E200-0xE000E23C Interrupt Set Pending Registers

§ ICPR

uint32_t Hwi_NVIC::ICPR[16]

0xE000E240-0xE000E7C reserved

§ RES_2C0

uint32_t Hwi_NVIC::RES_2C0[16]

0xE000E280-0xE000E2BC Interrupt Clear Pending Registers

§ IABR

uint32_t Hwi_NVIC::IABR[16]

0xE000E2C0-0xE000E2FC reserved

§ RES_340

uint32_t Hwi_NVIC::RES_340[16]

0xE000E300-0xE000E33C Interrupt Active Bit Registers

§ ITNS

uint32_t Hwi_NVIC::ITNS[16]

0xE000E340-0xE000E37C reserved

§ RES_3C0

uint32_t Hwi_NVIC::RES_3C0[16]

0xE000E380-0xE000E3BC Interrupt Target Non-Secure Registers

§ IPR

uint8_t Hwi_NVIC::IPR[492]

0xE000E3C0-0xE000E3FC reserved

§ RES_5F0

uint32_t Hwi_NVIC::RES_5F0[453]

0xE000E400-0xE000E5EC Interrupt Priority Registers

§ CPUIDBR

uint32_t Hwi_NVIC::CPUIDBR

0xE000E5F0-0xE000ECFC reserved

§ ICSR

uint32_t Hwi_NVIC::ICSR

0xE000ED00 CPUID Base Register

§ VTOR

uint32_t Hwi_NVIC::VTOR

0xE000ED04 Interrupt Control State Register

§ AIRCR

uint32_t Hwi_NVIC::AIRCR

0xE000ED08 Vector Table Offset Register

§ SCR

uint32_t Hwi_NVIC::SCR

0xE000ED0C Application Interrupt/Reset Control Register

§ CCR

uint32_t Hwi_NVIC::CCR

0xE000ED10 System Control Register

§ SHPR

uint8_t Hwi_NVIC::SHPR[12]

0xE000ED14 Configuration Control Register

§ SHCSR

uint32_t Hwi_NVIC::SHCSR

0xE000ED18 System Handlers 4-15 Priority Registers

§ MMFSR

uint8_t Hwi_NVIC::MMFSR

0xE000ED24 System Handler Control & State Register

§ BFSR

uint8_t Hwi_NVIC::BFSR

0xE000ED28 Memory Manage Fault Status Register

§ UFSR

uint16_t Hwi_NVIC::UFSR

0xE000ED29 Bus Fault Status Register

§ HFSR

uint32_t Hwi_NVIC::HFSR

0xE000ED2A Usage Fault Status Register

§ DFSR

uint32_t Hwi_NVIC::DFSR

0xE000ED2C Hard Fault Status Register

§ MMAR

uint32_t Hwi_NVIC::MMAR

0xE000ED30 Debug Fault Status Register

§ BFAR

uint32_t Hwi_NVIC::BFAR

0xE000ED34 Memory Manager Address Register

§ AFSR

uint32_t Hwi_NVIC::AFSR

0xE000ED38 Bus Fault Address Register

§ PFR0

uint32_t Hwi_NVIC::PFR0

0xE000ED3C Auxiliary Fault Status Register

§ PFR1

uint32_t Hwi_NVIC::PFR1

0xE000ED40 Processor Feature Register

§ DFR0

uint32_t Hwi_NVIC::DFR0

0xE000ED44 Processor Feature Register

§ AFR0

uint32_t Hwi_NVIC::AFR0

0xE000ED48 Debug Feature Register

§ MMFR0

uint32_t Hwi_NVIC::MMFR0

0xE000ED4C Auxiliary Feature Register

§ MMFR1

uint32_t Hwi_NVIC::MMFR1

0xE000ED50 Memory Model Fault Register0

§ MMFR2

uint32_t Hwi_NVIC::MMFR2

0xE000ED54 Memory Model Fault Register1

§ MMFR3

uint32_t Hwi_NVIC::MMFR3

0xE000ED58 Memory Model Fault Register2

§ ISAR0

uint32_t Hwi_NVIC::ISAR0

0xE000ED5C Memory Model Fault Register3

§ ISAR1

uint32_t Hwi_NVIC::ISAR1

0xE000ED60 ISA Feature Register0

§ ISAR2

uint32_t Hwi_NVIC::ISAR2

0xE000ED64 ISA Feature Register1

§ ISAR3

uint32_t Hwi_NVIC::ISAR3

0xE000ED68 ISA Feature Register2

§ ISAR4

uint32_t Hwi_NVIC::ISAR4

0xE000ED6C ISA Feature Register3

§ ISAR5

uint32_t Hwi_NVIC::ISAR5

0xE000ED70 ISA Feature Register4

§ CLIDR

uint32_t Hwi_NVIC::CLIDR

0xE000ED74 ISA Feature Register5

§ CTR

uint32_t Hwi_NVIC::CTR

0xE000ED78 Cache Level ID Register

§ CCSIDR

uint32_t Hwi_NVIC::CCSIDR

0xE000ED7C Cache Type Register

§ CSSELR

uint32_t Hwi_NVIC::CSSELR

0xE000ED80 Current Cache Size ID Register

§ CPACR

uint32_t Hwi_NVIC::CPACR

0xE000ED84 Cache Size Selection Register

§ NSACR

uint32_t Hwi_NVIC::NSACR

0xE000ED88 Coprocessor Access Control Register

§ MPU_TYPE

uint32_t Hwi_NVIC::MPU_TYPE

0xE000ED8C Non-secure Access Control Register

§ MPU_CTRL

uint32_t Hwi_NVIC::MPU_CTRL

0xE000ED90 MPU Type Register

§ MPU_RNR

uint32_t Hwi_NVIC::MPU_RNR

0xE000ED94 MPU Control Register

§ MPU_RBAR

uint32_t Hwi_NVIC::MPU_RBAR

0xE000ED98 MPU Region Number Register

§ MPU_RLAR

uint32_t Hwi_NVIC::MPU_RLAR

0xE000ED9C MPU Region Base Address Register

§ MPU_RBAR_An

uint32_t Hwi_NVIC::MPU_RBAR_An

0xE000EDA0 MPU Region Limit Address Register

§ MPU_RLAR_An

uint32_t Hwi_NVIC::MPU_RLAR_An

0xE000EDA4 MPU Region Base Address Register Alias n

§ RES_DAC

uint32_t Hwi_NVIC::RES_DAC[5]

0xE000EDA8 MPU Region Limit Address Register Alias n

§ MPU_MAIR0

uint32_t Hwi_NVIC::MPU_MAIR0

0xE000EDAC-0xE000EDBC

§ MPU_MAIR1

uint32_t Hwi_NVIC::MPU_MAIR1

0xE000EDC0 MPU Memory Attribute Indirection Register 0

§ RES_DC8

uint32_t Hwi_NVIC::RES_DC8[2]

0xE000EDC4 MPU Memory Attribute Indirection Register 1

§ SAU_CTRL

uint32_t Hwi_NVIC::SAU_CTRL

0xE000EDC8-0xE000EDCC Reserved

§ SAU_TYPE

uint32_t Hwi_NVIC::SAU_TYPE

0xE000EDD0 SAU Control Register

§ SAU_RNR

uint32_t Hwi_NVIC::SAU_RNR

0xE000EDD4 SAU Type Register

§ SAU_RBAR

uint32_t Hwi_NVIC::SAU_RBAR

0xE000EDD8 SAU Region Number Register

§ SAU_RLAR

uint32_t Hwi_NVIC::SAU_RLAR

0xE000EDDC SAU Region Base Address Register

§ SFSR

uint32_t Hwi_NVIC::SFSR

0xE000EDE0 SAU Region Limit Address Register

§ SFAR

uint32_t Hwi_NVIC::SFAR

0xE000EDE4 Secure Fault Status Register

§ RES_DEC

uint32_t Hwi_NVIC::RES_DEC

0xE000EDE8 Secure Fault Address Register

§ DHCSR

uint32_t Hwi_NVIC::DHCSR

0xE000EDEC Reserved

§ DCRSR

uint32_t Hwi_NVIC::DCRSR

0xE000EDF0 Debug Halting Control and Status Register

§ DCRDR

uint32_t Hwi_NVIC::DCRDR

0xE000EDF4 Debug Core Register Select Register

§ DEMCR

uint32_t Hwi_NVIC::DEMCR

0xE000EDF8 Debug Core Register Data Register

§ RES_E00

uint32_t Hwi_NVIC::RES_E00

0xE000EDFC Debug Exception and Monitor Control Register

§ DAUTHCTRL

uint32_t Hwi_NVIC::DAUTHCTRL

0xE000EE00 Reserved

§ DSCSR

uint32_t Hwi_NVIC::DSCSR

0xE000EE04 Debug Authentication Control Register

§ RES_E0C

uint32_t Hwi_NVIC::RES_E0C[61]

0xE000EE08 Debug Security Control and Status Register

§ STI

uint32_t Hwi_NVIC::STI

0xE000EE0C-0xE000EEFC reserved

§ RES_F04

uint32_t Hwi_NVIC::RES_F04[12]

0xE000EF00 Software Trigger Interrupt Register

§ FPCCR

uint32_t Hwi_NVIC::FPCCR

0xE000EF04-0xE000EF30 reserved

§ FPCAR

uint32_t Hwi_NVIC::FPCAR

0xE000EF34 FP Context Control Register

§ FPDSCR

uint32_t Hwi_NVIC::FPDSCR

0xE000EF38 FP Context Address Register

§ MVFR0

uint32_t Hwi_NVIC::MVFR0

0xE000EF3C FP Default Status Control Register

§ MVFR1

uint32_t Hwi_NVIC::MVFR1

0xE000EF40 Media & FP Feature Register0

§ MVFR2

uint32_t Hwi_NVIC::MVFR2

0xE000EF44 Media & FP Feature Register1

§ RES_F48

uint32_t Hwi_NVIC::RES_F48

0xE000EF48 Media & FP Feature Register2

§ ICIALLU

uint32_t Hwi_NVIC::ICIALLU

0xE000EF4C reserved

§ RES_F54

uint32_t Hwi_NVIC::RES_F54

0xE000EF50 Instruction Cache Invalidate All to PoU

§ ICIMVAU

uint32_t Hwi_NVIC::ICIMVAU

0xE000EF54 reserved

§ DCIMVAC

uint32_t Hwi_NVIC::DCIMVAC

0xE000EF58 Instruction Cache line Invalidate by Address to PoU

§ DCISW

uint32_t Hwi_NVIC::DCISW

0xE000EF5C Data Cache line Invalidate by Address to PoC

§ DCCMVAU

uint32_t Hwi_NVIC::DCCMVAU

0xE000EF60 Data Cache line Invalidate by Set/Way

§ DCCMVAC

uint32_t Hwi_NVIC::DCCMVAC

0xE000EF64 Data Cache line Clean by address to PoU

§ DCCSW

uint32_t Hwi_NVIC::DCCSW

0xE000EF68 Data Cache line Clean by Address to PoC

§ DCCIMVAC

uint32_t Hwi_NVIC::DCCIMVAC

0xE000EF6C Data Cache Clean line by Set/Way

§ DCCISW

uint32_t Hwi_NVIC::DCCISW

0xE000EF70 Data Cache line Clean and Invalidate by Address to PoC

§ BPIALL

uint32_t Hwi_NVIC::BPIALL

0xE000EF74 Data Cache line Clean and Invalidate by Set/Way

§ RES_F7C

uint32_t Hwi_NVIC::RES_F7C[13]

0xE000EF78 Branch Predictor Invalidate All

§ DLAR

uint32_t Hwi_NVIC::DLAR

0xE000EF7C-0xE000EFAC reserved

§ DLSR

uint32_t Hwi_NVIC::DLSR

0xE000EFB0 SCS Software Lock Access Register

§ DAUTHSTATUS

uint32_t Hwi_NVIC::DAUTHSTATUS

0xE000EFB4 SCS Software Lock Status Register

§ DDEVARCH

uint32_t Hwi_NVIC::DDEVARCH

0xE000EFB8 Debug Authentication Status Register

§ RES_FC0

uint32_t Hwi_NVIC::RES_FC0[3]

0xE000EFBC SCS Device Architecture Register

§ DDEVTYPE

uint32_t Hwi_NVIC::DDEVTYPE

0xE000EFC0-0xE000EFC8 reserved

§ DPIDR4

uint32_t Hwi_NVIC::DPIDR4

0xE000EFCC SCS Device Type Register

§ DPIDR5

uint32_t Hwi_NVIC::DPIDR5

0xE000EFD0 SCS Peripheral Identification Register 4

§ DPIDR6

uint32_t Hwi_NVIC::DPIDR6

0xE000EFD4 SCS Peripheral Identification Register 5

§ DPIDR7

uint32_t Hwi_NVIC::DPIDR7

0xE000EFD8 SCS Peripheral Identification Register 6

§ DPIDR0

uint32_t Hwi_NVIC::DPIDR0

0xE000EFDC SCS Peripheral Identification Register 7

§ DPIDR1

uint32_t Hwi_NVIC::DPIDR1

0xE000EFE0 SCS Peripheral Identification Register 0

§ DPIDR2

uint32_t Hwi_NVIC::DPIDR2

0xE000EFE4 SCS Peripheral Identification Register 1

§ DPIDR3

uint32_t Hwi_NVIC::DPIDR3

0xE000EFE8 SCS Peripheral Identification Register 2

§ DCIDR0

uint32_t Hwi_NVIC::DCIDR0

0xE000EFEC SCS Peripheral Identification Register 3

§ DCIDR1

uint32_t Hwi_NVIC::DCIDR1

0xE000EFF0 SCS Component Identification Register 0

§ DCIDR2

uint32_t Hwi_NVIC::DCIDR2

0xE000EFF4 SCS Component Identification Register 1

§ DCIDR3

uint32_t Hwi_NVIC::DCIDR3

0xE000EFF8 SCS Component Identification Register 2

The documentation for this struct was generated from the following file:

ti/sysbios/family/arm/v8m/Hwi.h

Data Fields