UART2CC26X2 Hardware attributes. More...
#include <UART2CC26X2.h>
Data Fields | |
UART2_BASE_HWATTRS volatile tDMAControlTable * | dmaTxTableEntryPri |
volatile tDMAControlTable * | dmaRxTableEntryPri |
uint32_t | txChannelMask |
uint32_t | rxChannelMask |
PowerCC26XX_Resource | powerId |
int32_t | txPinMux |
int32_t | rxPinMux |
int32_t | ctsPinMux |
int32_t | rtsPinMux |
UART2CC26X2_FifoThreshold | txIntFifoThr |
UART2CC26X2_FifoThreshold | rxIntFifoThr |
UART2CC26X2 Hardware attributes.
The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:
intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). The CC26x2 uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).
(7 << 5) will apply the lowest priority. (1 << 5) will apply the highest priority.
Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.
A sample structure is shown below:
To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE.
UART2_BASE_HWATTRS volatile tDMAControlTable* UART2CC26X2_HWAttrs::dmaTxTableEntryPri |
volatile tDMAControlTable* UART2CC26X2_HWAttrs::dmaRxTableEntryPri |
uDMA controlTable primary tx entry
uint32_t UART2CC26X2_HWAttrs::txChannelMask |
uDMA controlTable primary rx entry
uint32_t UART2CC26X2_HWAttrs::rxChannelMask |
Mask for uDMA tx channel number (1 << channel number)
PowerCC26XX_Resource UART2CC26X2_HWAttrs::powerId |
Mask for uDMA rx channel number (1 << channel number)
int32_t UART2CC26X2_HWAttrs::txPinMux |
Power driver ID of the UART instance
int32_t UART2CC26X2_HWAttrs::rxPinMux |
Tx PIN mux value
int32_t UART2CC26X2_HWAttrs::ctsPinMux |
Tx PIN mux value
int32_t UART2CC26X2_HWAttrs::rtsPinMux |
CTS PIN mux value for flow control
UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::txIntFifoThr |
RTS PIN mux value for flow control
UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::rxIntFifoThr |
UART TX interrupt FIFO threshold select