479 uint32_t ui32TrimValue;
484 if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
485 AON_PMCTL_PWRCTL_EXT_REG_MODE)
491 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
494 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
496 ui32Value = ((ui32TrimValue &
497 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
498 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
499 FLASH_CFG_STANDBY_MODE_SEL_S;
501 ui32Value |= ((ui32TrimValue &
502 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
503 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
504 FLASH_CFG_STANDBY_PW_SEL_S;
508 ui32Value |= ((ui32TrimValue &
509 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
510 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
511 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
512 FLASH_CFG_DIS_IDLE_S;
514 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
515 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
516 FLASH_CFG_STANDBY_PW_SEL_M |
517 FLASH_CFG_DIS_STANDBY_M |
518 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
521 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
524 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
530 ui32Value = ((ui32TrimValue &
531 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
532 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
533 FLASH_FSEQPMP_VIN_AT_X_S;
538 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
539 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
541 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
544 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
545 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
546 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
547 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
548 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
549 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
557 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
560 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
562 ui32Value = ((ui32TrimValue &
563 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
564 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
565 FLASH_CFG_STANDBY_MODE_SEL_S;
567 ui32Value |= ((ui32TrimValue &
568 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
569 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
570 FLASH_CFG_STANDBY_PW_SEL_S;
574 ui32Value |= ((ui32TrimValue &
575 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
576 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
577 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
578 FLASH_CFG_DIS_IDLE_S;
580 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
581 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
582 FLASH_CFG_STANDBY_PW_SEL_M |
583 FLASH_CFG_DIS_STANDBY_M |
584 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
587 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
590 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
596 ui32Value = (((ui32TrimValue &
597 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
598 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
599 FLASH_FSEQPMP_VIN_AT_X_S);
604 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
605 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
607 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
610 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
611 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
612 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
613 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
614 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
615 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
#define FCFG1_OFFSET
Definition: flash.h:151