CC26xx Driver Library
Macros | Typedefs | Functions | Variables
flash.c File Reference
#include "../inc/hw_types.h"
#include "../inc/hw_ccfg.h"
#include "flash.h"
#include "rom.h"
#include "chipinfo.h"

Macros

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG
 
#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0
 
#define CCFG_SIZE_SECURITY   0x00000014
 
#define CCFG_SIZE_SECT_PROT   0x00000004
 

Typedefs

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)
 
typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)
 

Functions

static void SetReadMode (void)
 
void FlashPowerModeSet (uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)
 Set power mode. More...
 
uint32_t FlashPowerModeGet (void)
 Get current configured power mode. More...
 
void FlashProtectionSet (uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)
 Set sector protection. More...
 
uint32_t FlashProtectionGet (uint32_t ui32SectorAddress)
 Get sector protection. More...
 
uint32_t FlashProtectionSave (uint32_t ui32SectorAddress)
 Save sector protection to make it permanent. More...
 
uint32_t FlashSectorErase (uint32_t ui32SectorAddress)
 Erase a flash sector. More...
 
uint32_t FlashProgram (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 Programs unprotected flash sectors in the main bank. More...
 
bool FlashEfuseReadRow (uint32_t *pui32EfuseData, uint32_t ui32RowAddress)
 Reads efuse data from specified row. More...
 
void FlashDisableSectorsForWrite (void)
 Disables all sectors for erase and programming on the active bank. More...
 
uint32_t MemBusWrkAroundHapiProgramFlash (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 
uint32_t MemBusWrkAroundHapiEraseSector (uint32_t ui32Address)
 

Variables

const uint8_t g_pui8CcfgDefaultSec []
 

Macro Definition Documentation

#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0

Referenced by FlashProtectionSave().

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG
#define CCFG_SIZE_SECT_PROT   0x00000004

Referenced by FlashProtectionSave().

#define CCFG_SIZE_SECURITY   0x00000014

Typedef Documentation

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)
typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)

Function Documentation

uint32_t MemBusWrkAroundHapiEraseSector ( uint32_t  ui32Address)
650 {
651  uint32_t ui32ErrorReturn;
652 
653  FlashSectorErasePointer_t FuncPointer;
654  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4));
655 
656  // Call ROM function
657  FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr);
658  ui32ErrorReturn = FuncPointer(ui32Address);
659 
660  // Enable standby in flash bank since ROM function might have disabled it
661  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
662 
663  // Return status of operation.
664  return(ui32ErrorReturn);
665 }
FlashSectorErasePointer_t
uint32_t(* FlashSectorErasePointer_t)(uint32_t)
Definition: flash.c:99
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:59
uint32_t MemBusWrkAroundHapiProgramFlash ( uint8_t *  pui8DataBuffer,
uint32_t  ui32Address,
uint32_t  ui32Count 
)
627 {
628  uint32_t ui32ErrorReturn;
629  FlashPrgPointer_t FuncPointer;
630  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4));
631 
632  // Call ROM function
633  FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr);
634  ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
635 
636  // Enable standby in flash bank since ROM function might have disabled it
637  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
638 
639  // Return status of operation.
640  return(ui32ErrorReturn);
641 }
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:59
FlashPrgPointer_t
uint32_t(* FlashPrgPointer_t)(uint8_t *, uint32_t, uint32_t)
Definition: flash.c:97
static void SetReadMode ( void  )
static

Referenced by FlashDisableSectorsForWrite().

478 {
479  uint32_t ui32TrimValue;
480  uint32_t ui32Value;
481 
482  // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
483  // VIN_AT_X and VIN_BY_PASS for read mode
484  if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
485  AON_PMCTL_PWRCTL_EXT_REG_MODE)
486  {
487  // Select trim values for external regulator mode:
488  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
489  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
490  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
491  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
492 
493  ui32TrimValue =
494  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
495 
496  ui32Value = ((ui32TrimValue &
497  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
498  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
499  FLASH_CFG_STANDBY_MODE_SEL_S;
500 
501  ui32Value |= ((ui32TrimValue &
502  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
503  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
504  FLASH_CFG_STANDBY_PW_SEL_S;
505 
506  // Configure DIS_STANDBY (OTP offset 0x308 bit 4).
507  // Configure DIS_IDLE (OTP offset 0x308 bit 3).
508  ui32Value |= ((ui32TrimValue &
509  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
510  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
511  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
512  FLASH_CFG_DIS_IDLE_S;
513 
514  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
515  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
516  FLASH_CFG_STANDBY_PW_SEL_M |
517  FLASH_CFG_DIS_STANDBY_M |
518  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
519 
520  // Check if sample and hold functionality is disabled.
521  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
522  {
523  // Wait for disabled sample and hold functionality to be stable.
524  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
525  {
526  }
527  }
528 
529  // Configure VIN_AT_X (OTP offset 0x308 bits 2:0)
530  ui32Value = ((ui32TrimValue &
531  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
532  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
533  FLASH_FSEQPMP_VIN_AT_X_S;
534 
535  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
536  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
537  // VIN_BY_PASS should be 1
538  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
539  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
540  {
541  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
542  }
543 
544  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
545  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
546  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
547  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
548  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
549  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
550  }
551  else
552  {
553  // Select trim values for internal regulator mode:
554  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
555  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
556  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
557  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
558 
559  ui32TrimValue =
560  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
561 
562  ui32Value = ((ui32TrimValue &
563  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
564  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
565  FLASH_CFG_STANDBY_MODE_SEL_S;
566 
567  ui32Value |= ((ui32TrimValue &
568  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
569  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
570  FLASH_CFG_STANDBY_PW_SEL_S;
571 
572  // Configure DIS_STANDBY (OTP offset 0x308 bit 12).
573  // Configure DIS_IDLE (OTP offset 0x308 bit 11).
574  ui32Value |= ((ui32TrimValue &
575  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
576  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
577  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
578  FLASH_CFG_DIS_IDLE_S;
579 
580  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
581  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
582  FLASH_CFG_STANDBY_PW_SEL_M |
583  FLASH_CFG_DIS_STANDBY_M |
584  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
585 
586  // Check if sample and hold functionality is disabled.
587  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
588  {
589  // Wait for disabled sample and hold functionality to be stable.
590  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
591  {
592  }
593  }
594 
595  // Configure VIN_AT_X (OTP offset 0x308 bits 10:8)
596  ui32Value = (((ui32TrimValue &
597  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
598  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
599  FLASH_FSEQPMP_VIN_AT_X_S);
600 
601  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
602  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
603  // VIN_BY_PASS should be 1
604  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
605  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
606  {
607  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
608  }
609 
610  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
611  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
612  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
613  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
614  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
615  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
616  }
617 }
FCFG1_OFFSET
#define FCFG1_OFFSET
Definition: flash.h:151

Variable Documentation

const uint8_t g_pui8CcfgDefaultSec[]
Initial value:
= {0xFF, 0xFF, 0xFF, 0xC5,
0xFF, 0xFF, 0xFF, 0xFF,
0xC5, 0xFF, 0xFF, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF
}