Data Fields
UART2CC26X2_HWAttrs Struct Reference

UART2CC26X2 Hardware attributes. More...

#include <UART2CC26X2.h>

Data Fields

uint32_t baseAddr
 
int intNum
 
uint8_t intPriority
 
uint32_t flowControl
 
uint8_t rxPin
 
uint8_t txPin
 
uint8_t ctsPin
 
uint8_t rtsPin
 
uint32_t rxChannelMask
 
uint32_t txChannelMask
 
UART2CC26X2_FifoThreshold txIntFifoThr
 
UART2CC26X2_FifoThreshold rxIntFifoThr
 

Detailed Description

UART2CC26X2 Hardware attributes.

The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). The CC26x2 uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).

  (7 << 5) will apply the lowest priority.
  (1 << 5) will apply the highest priority.

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2CC26X2_HWAttrs uartCC26X2HWAttrs[] = {
{
.baseAddr = UARTA0_BASE,
.intNum = INT_UART0_COMB,
.intPriority = (~0),
.rxPin = IOID_2,
.txPin = IOID_3,
.rxChannelMask = 1 << UDMA_CHAN_UART0_RX,
.txChannelMask = 1 << UDMA_CHAN_UART0_TX,
},
{
.baseAddr = UART1_BASE,
.intNum = INT_UART1_COMB,
.intPriority = (~0),
.rxChannelMask = 1 << UDMA_CHAN_UART1_RX,
.txChannelMask = 1 << UDMA_CHAN_UART1_TX,
},
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2CC26X2_FLOWCTL_HARDWARE.

Field Documentation

§ baseAddr

uint32_t UART2CC26X2_HWAttrs::baseAddr

UART Peripheral's base address

§ intNum

int UART2CC26X2_HWAttrs::intNum

UART Peripheral's interrupt vector

§ intPriority

uint8_t UART2CC26X2_HWAttrs::intPriority

UART Peripheral's interrupt priority

§ flowControl

uint32_t UART2CC26X2_HWAttrs::flowControl

Hardware flow control setting

§ rxPin

uint8_t UART2CC26X2_HWAttrs::rxPin

UART RX pin assignment

§ txPin

uint8_t UART2CC26X2_HWAttrs::txPin

UART TX pin assignment

§ ctsPin

uint8_t UART2CC26X2_HWAttrs::ctsPin

UART clear to send (CTS) pin assignment

§ rtsPin

uint8_t UART2CC26X2_HWAttrs::rtsPin

UART request to send (RTS) pin assignment

§ rxChannelMask

uint32_t UART2CC26X2_HWAttrs::rxChannelMask

Mask for UDMA channel number for RX data (1 << channel number)

§ txChannelMask

uint32_t UART2CC26X2_HWAttrs::txChannelMask

Mask for UDMA channel number for TX data (1 << channel number)

§ txIntFifoThr

UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::txIntFifoThr

UART TX interrupt FIFO threshold select

§ rxIntFifoThr

UART2CC26X2_FifoThreshold UART2CC26X2_HWAttrs::rxIntFifoThr

UART RX interrupt FIFO threshold select


The documentation for this struct was generated from the following file:
© Copyright 1995-2020, Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy policy | Terms of use | Terms of sale