Instance: AUX_AIODIO1
Component: AUX_AIODIO
Base address: 0x400CD000
AUX Analog Digital Input Output Controller (AUX_AIODIO) controls the general purpose input output pins of the AUX domain. These pins are referenced as AUXIO and can:
- be connected to analog AUX modules, such as comparators and ADC.
- be used by AUX_SCE.
- connect to AUX_SPIM SCLK, MISO and MOSI signals.
- connect to the asynchronous AUX event bus.
Enabled digital inputs are synchronized at SCE clock rate.
Note that the IO mapping in the AUX domain is different from the IO mapping in the MCU domain. This means that AUXIO[n] does not map to DIO[n]. AUXIO-DIO remapping is handled by Sensor Controller Studio.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C D000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C D004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C D008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x400C D00C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C D010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C D014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C D018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C D01C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x400C D020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C D024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x400C D028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x400C D02C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C D030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C D034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C D038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x400C D03C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x400C D040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x400C D044 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C D000 | Instance | 0x400C D000 |
Description | Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||
15:14 | IO7 | Selects mode for AUXIO[8i+7].
|
RW | 0b00 | |||||||||||||||||
13:12 | IO6 | Selects mode for AUXIO[8i+6].
|
RW | 0b00 | |||||||||||||||||
11:10 | IO5 | Selects mode for AUXIO[8i+5].
|
RW | 0b00 | |||||||||||||||||
9:8 | IO4 | Selects mode for AUXIO[8i+4].
|
RW | 0b00 | |||||||||||||||||
7:6 | IO3 | Selects mode for AUXIO[8i+3].
|
RW | 0b00 | |||||||||||||||||
5:4 | IO2 | Select mode for AUXIO[8i+2].
|
RW | 0b00 | |||||||||||||||||
3:2 | IO1 | Select mode for AUXIO[8i+1].
|
RW | 0b00 | |||||||||||||||||
1:0 | IO0 | Select mode for AUXIO[8i+0].
|
RW | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C D004 | Instance | 0x400C D004 |
Description | General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. |
RW | 0x00 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C D008 | Instance | 0x400C D008 |
Description | Input Output Peripheral Output Enable This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in IOnPSEL. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. |
RW | 0x00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C D00C | Instance | 0x400C D00C |
Description | General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. |
RW | 0x00 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C D010 | Instance | 0x400C D010 |
Description | General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. | RO | 0x00 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C D014 | Instance | 0x400C D014 |
Description | General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C D018 | Instance | 0x400C D018 |
Description | General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C D01C | Instance | 0x400C D01C |
Description | General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | IO7_0 | Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. |
RW | 0x00 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C D020 | Instance | 0x400C D020 |
Description | Input Output 0 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1. To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x400C D024 | Instance | 0x400C D024 |
Description | Input Output 1 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1. To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x400C D028 | Instance | 0x400C D028 |
Description | Input Output 2 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1. To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set.
|
RW | 0b000 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x400C D02C | Instance | 0x400C D02C |
Description | Input Output 3 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1. To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x400C D030 | Instance | 0x400C D030 |
Description | Input Output 4 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1. To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x400C D034 | Instance | 0x400C D034 |
Description | Input Output 5 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1. To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x400C D038 | Instance | 0x400C D038 |
Description | Input Output 6 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1. To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set.
|
RW | 0b000 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x400C D03C | Instance | 0x400C D03C |
Description | Input Output 7 Peripheral Select This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1. To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0. In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | SRC | Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set.
|
RW | 0b000 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x400C D040 | Instance | 0x400C D040 |
Description | Input Output Mode Low This is an alias register for IOMODE.IO0 thru IOMODE.IO3. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:6 | IO3 | See IOMODE.IO3. | RW | 0b00 | ||
5:4 | IO2 | See IOMODE.IO2. | RW | 0b00 | ||
3:2 | IO1 | See IOMODE.IO1. | RW | 0b00 | ||
1:0 | IO0 | See IOMODE.IO0. | RW | 0b00 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x400C D044 | Instance | 0x400C D044 |
Description | Input Output Mode High This is an alias register for IOMODE.IO4 thru IOMODE.IO7. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:6 | IO7 | See IOMODE.IO7. | RW | 0b00 | ||
5:4 | IO6 | See IOMODE.IO6. | RW | 0b00 | ||
3:2 | IO5 | See IOMODE.IO5. | RW | 0b00 | ||
1:0 | IO4 | See IOMODE.IO4. | RW | 0b00 |
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