AON_PMCTL

Instance: AON_PMCTL
Component: AON_PMCTL
Base address: 0x40090000


This component control the Power Management controller residing in the AON domain.

Note: This module is only supporting 32 bit Read Write access from MCU

TOP:AON_PMCTL Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

AUXSCECLK

RW

32

0x0000 0000

0x0000 0004

0x4009 0004

RAMCFG

RW

32

0x0001 000F

0x0000 0008

0x4009 0008

PWRCTL

RW

32

0x0000 0000

0x0000 0010

0x4009 0010

PWRSTAT

RW

32

0x03C0 0003

0x0000 0014

0x4009 0014

SHUTDOWN

RW

32

0x0000 0000

0x0000 0018

0x4009 0018

RECHARGECFG

RW

32

0xC000 0000

0x0000 001C

0x4009 001C

RECHARGESTAT

RW

32

0x0000 0000

0x0000 0020

0x4009 0020

OSCCFG

RW

32

0x0000 0000

0x0000 0024

0x4009 0024

RESETCTL

RW

32

0x0000 01C0

0x0000 0028

0x4009 0028

SLEEPCTL

RW

32

0x0000 0000

0x0000 002C

0x4009 002C

JTAGCFG

RW

32

0x0000 0100

0x0000 0034

0x4009 0034

JTAGUSERCODE

RW

32

0x0B99 A02F

0x0000 003C

0x4009 003C

TOP:AON_PMCTL Register Descriptions

TOP:AON_PMCTL:AUXSCECLK

Address Offset 0x0000 0004
Physical Address 0x4009 0004 Instance 0x4009 0004
Description AUX SCE Clock Management

This register contains bitfields that are relevant for setting up the clock to the AUX domain.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 PD_SRC Selects the clock source for the AUX domain when AUX is in powerdown mode.
Note: Switching the clock source is guaranteed to be glitch-free
Value ENUM Name Description
0x0 NO_CLOCK No clock
0x1 SCLK_LF LF clock (SCLK_LF )
RW 0
7:1 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 SRC Selects the clock source for the AUX domain when AUX is in active mode.
Note: Switching the clock source is guaranteed to be glitch-free
Value ENUM Name Description
0x0 SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2)
0x1 SCLK_MF MF Clock (SCLK_MF)
RW 0

TOP:AON_PMCTL:RAMCFG

Address Offset 0x0000 0008
Physical Address 0x4009 0008 Instance 0x4009 0008
Description RAM Configuration

This register contains power management related configuration for the SRAM in the MCU and AUX domain.
Type RW
Bits Field Name Description Type Reset
31:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000
17 AUX_SRAM_PWR_OFF Internal. Only to be used through TI provided API. RW 0
16 AUX_SRAM_RET_EN Internal. Only to be used through TI provided API. RW 1
15:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
3:0 BUS_SRAM_RET_EN MCU SRAM is partitioned into 5 banks . This register controls which of the banks that has retention during MCU Bus domain power off
Value ENUM Name Description
0x0 RET_NONE Retention is disabled
0x1 RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1
0x3 RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2
0x7 RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3
0xF RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4
RW 0xF

TOP:AON_PMCTL:PWRCTL

Address Offset 0x0000 0010
Physical Address 0x4009 0010 Instance 0x4009 0010
Description Power Management Control

This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000 0000 0000 0000 0000 0000 0000
2 DCDC_ACTIVE Select to use DCDC regulator for VDDR in active mode

0: Use GLDO for regulation of VDDR in active mode.
1: Use DCDC for regulation of VDDR in active mode.

DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active mode		 RW 0
1 EXT_REG_MODE Status of source for VDDRsupply:

0: DCDC or GLDO are generating VDDR
1: DCDC and GLDO are bypassed and an external regulator supplies VDDR		 RO 0
0 DCDC_EN Select to use DCDC regulator during recharge of VDDR

0: Use GLDO for recharge of VDDR
1: Use DCDC for recharge of VDDR

Note: This bitfield should be set to the same as DCDC_ACTIVE		 RW 0

TOP:AON_PMCTL:PWRSTAT

Address Offset 0x0000 0014
Physical Address 0x4009 0014 Instance 0x4009 0014
Description AON Power and Reset Status

This register is used to monitor various power management related signals in AON. All other signals than JTAG_PD_ON, AUX_BUS_RESET_DONE, and AUX_RESET_DONE are for test, calibration and debug purpose only.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b0 0000 0111 1000 0000 0000 0000 0000
2 JTAG_PD_ON Indicates JTAG power state:

0: JTAG is powered off
1: JTAG is powered on		 RO 0
1 AUX_BUS_RESET_DONE Indicates Reset Done from AUX Bus:

0: AUX Bus is being reset
1: AUX Bus reset is released		 RO 1
0 AUX_RESET_DONE Indicates Reset Done from AUX:

0: AUX is being reset
1: AUX reset is released		 RO 1

TOP:AON_PMCTL:SHUTDOWN

Address Offset 0x0000 0018
Physical Address 0x4009 0018 Instance 0x4009 0018
Description Shutdown Control

This register contains bitfields required for entering shutdown mode
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Shutdown control.

0: Do not write 0 to this bit.
1: Immediately start the process to enter shutdown mode		 RW 0

TOP:AON_PMCTL:RECHARGECFG

Address Offset 0x0000 001C
Physical Address 0x4009 001C Instance 0x4009 001C
Description Recharge Controller Configuration

This register sets all relevant parameters for controlling the recharge algorithm.
Type RW
Bits Field Name Description Type Reset
31:30 MODE Selects recharge algorithm for VDDR when the system is running on the uLDO
Value ENUM Name Description
0x0 OFF Recharge disabled
0x1 STATIC Static timer
0x2 ADAPTIVE Adaptive timer
0x3 COMPARATOR External recharge comparator.
Note that the clock to the recharge comparator must be enabled, [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], before selecting this recharge algorithm.
RW 0b11
29:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
23:20 C2 Internal. Only to be used through TI provided API. RW 0x0
19:16 C1 Internal. Only to be used through TI provided API. RW 0x0
15:11 MAX_PER_M Internal. Only to be used through TI provided API. RW 0b0 0000
10:8 MAX_PER_E Internal. Only to be used through TI provided API. RW 0b000
7:3 PER_M Internal. Only to be used through TI provided API. RW 0b0 0000
2:0 PER_E Internal. Only to be used through TI provided API. RW 0b000

TOP:AON_PMCTL:RECHARGESTAT

Address Offset 0x0000 0020
Physical Address 0x4009 0020 Instance 0x4009 0020
Description Recharge Controller Status

This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug.
Type RW
Bits Field Name Description Type Reset
31:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000
19:16 VDDR_SMPLS The last 4 VDDR samples.

For each bit:
0: VDDR was below VDDR_OK threshold when recharge started
1: VDDR was above VDDR_OK threshold when recharge started

The register is updated prior to every recharge period with a shift left, and bit 0 is updated with the last VDDR sample.		 RO 0x0
15:0 MAX_USED_PER Shows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started. This register can be used as an indication of the leakage current during standby.

This bitfield is cleared to 0 when writing this register.		 RW 0x0000

TOP:AON_PMCTL:OSCCFG

Address Offset 0x0000 0024
Physical Address 0x4009 0024 Instance 0x4009 0024
Description Oscillator Configuration

This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:3 PER_M Internal. Only to be used through TI provided API. RW 0b0 0000
2:0 PER_E Internal. Only to be used through TI provided API. RW 0b000

TOP:AON_PMCTL:RESETCTL

Address Offset 0x0000 0028
Physical Address 0x4009 0028 Instance 0x4009 0028
Description Reset Management

This register contains bitfields related to system reset such as reset source and reset request and control of brown out resets.
Type RW
Bits Field Name Description Type Reset
31 SYSRESET Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again.

0: No effect
1: Generate system reset. Appears as SYSRESET in RESET_SRC		 WO 0
30:26 RESERVED26 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
25 BOOT_DET_1_CLR Internal. Only to be used through TI provided API. WO 0
24 BOOT_DET_0_CLR Internal. Only to be used through TI provided API. WO 0
23:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
17 BOOT_DET_1_SET Internal. Only to be used through TI provided API. WO 0
16 BOOT_DET_0_SET Internal. Only to be used through TI provided API. WO 0
15 WU_FROM_SD A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low)

Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.

0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC
1: A wakeup has occurred from SHUTDOWN

Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.		 RO 0
14 GPIO_WU_FROM_SD A wakeup from SHUTDOWN on an IO event has occurred

Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.

0: The wakeup did not occur from SHUTDOWN on an IO event
1: A wakeup from SHUTDOWN occurred from an IO event

The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well.

Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.		 RO 0
13 BOOT_DET_1 Internal. Only to be used through TI provided API. RO 0
12 BOOT_DET_0 Internal. Only to be used through TI provided API. RO 0
11:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b000
8 VDDS_LOSS_EN Controls reset generation in case VDDS is lost

0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1
1: Brown out detect of VDDS generates system reset		 RW 1
7 VDDR_LOSS_EN Controls reset generation in case VDDR is lost

0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1
1: Brown out detect of VDDR generates system reset		 RW 1
6 VDD_LOSS_EN Controls reset generation in case VDD is lost

0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1
1: Brown out detect of VDD generates system reset		 RW 1
5 CLK_LOSS_EN Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]

0: Clock loss is ignored
1: Clock loss generates system reset

Note: Clock loss reset generation must be disabled when changing clock source for SCLK_LF. Failure to do so may result in a spurious system reset. Clock loss reset generation is controlled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]		 RW 0
4 MCU_WARM_RESET Internal. Only to be used through TI provided API. RW 0
3:1 RESET_SRC Shows the root cause of the last system reset. More than the reported reset source can have been active during the last system reset but only the root cause is reported.

The capture feature is not rearmed until all off the possible reset sources have been released and the result has been copied to AON_PMCTL. During the copy and rearm process it is one 2MHz period in which and eventual new system reset will be reported as Power on reset regardless of the root cause.
Value ENUM Name Description
0x0 PWR_ON Power on reset
0x1 PIN_RESET Reset pin
0x2 VDDS_LOSS Brown out detect on VDDS
0x4 VDDR_LOSS Brown out detect on VDDR
0x5 CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect
0x6 SYSRESET Software reset via SYSRESET or hardware power management timeout detection.

Note: The hardware power management timeout circuit is always enabled.
0x7 WARMRESET Software reset via PRCM warm reset request
RO 0b000
0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0

TOP:AON_PMCTL:SLEEPCTL

Address Offset 0x0000 002C
Physical Address 0x4009 002C Instance 0x4009 002C
Description Sleep Control

This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 IO_PAD_SLEEP_DIS Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set).

0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations are latched. Inputs are transparent if pad is configured as input before IO_PAD_SLEEP_DIS is set to 1
1: I/O pad sleep mode is disabled

Application software must reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins.		 RW 0

TOP:AON_PMCTL:JTAGCFG

Address Offset 0x0000 0034
Physical Address 0x4009 0034 Instance 0x4009 0034
Description JTAG Configuration

This register contains control for configuration of the JTAG domain. This includes permissions for each TAP.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 JTAG_PD_FORCE_ON Controls JTAG Power domain power state:

0: Controlled exclusively by debug subsystem. (JTAG Power domain will be powered off unless a debugger is attached)
1: JTAG Power Domain is forced on, independent of debug subsystem.

Note: The reset value causes JTAG Power domain to be powered on by default. Software must clear this bit to turn off the JTAG Power domain		 RW 1
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0x00

TOP:AON_PMCTL:JTAGUSERCODE

Address Offset 0x0000 003C
Physical Address 0x4009 003C Instance 0x4009 003C
Description JTAG USERCODE

Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem.
Type RW
Bits Field Name Description Type Reset
31:0 USER_CODE 32-bit JTAG USERCODE register feeding main JTAG TAP
Note: This field can be locked by LOCKCFG.LOCK		 RW 0x0B99 A02F


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