IOC

Instance: IOC
Component: IOC
Base address: 0x40081000


IO Controller (IOC) - configures all the DIOs and resides in the MCU domain.

TOP:IOC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IOCFG0

RW

32

0x0000 6000

0x0000 0000

0x4008 1000

IOCFG1

RW

32

0x0000 6000

0x0000 0004

0x4008 1004

IOCFG2

RW

32

0x0000 6000

0x0000 0008

0x4008 1008

IOCFG3

RW

32

0x0000 6000

0x0000 000C

0x4008 100C

IOCFG4

RW

32

0x0000 6000

0x0000 0010

0x4008 1010

IOCFG5

RW

32

0x0000 6000

0x0000 0014

0x4008 1014

IOCFG6

RW

32

0x0000 6000

0x0000 0018

0x4008 1018

IOCFG7

RW

32

0x0000 6000

0x0000 001C

0x4008 101C

IOCFG8

RW

32

0x0000 6000

0x0000 0020

0x4008 1020

IOCFG9

RW

32

0x0000 6000

0x0000 0024

0x4008 1024

IOCFG10

RW

32

0x0000 6000

0x0000 0028

0x4008 1028

IOCFG11

RW

32

0x0000 6000

0x0000 002C

0x4008 102C

IOCFG12

RW

32

0x0000 6000

0x0000 0030

0x4008 1030

IOCFG13

RW

32

0x0000 6000

0x0000 0034

0x4008 1034

IOCFG14

RW

32

0x0000 6000

0x0000 0038

0x4008 1038

IOCFG15

RW

32

0x0000 6000

0x0000 003C

0x4008 103C

IOCFG16

RW

32

0x0008 6000

0x0000 0040

0x4008 1040

IOCFG17

RW

32

0x0010 6000

0x0000 0044

0x4008 1044

IOCFG18

RW

32

0x0000 6000

0x0000 0048

0x4008 1048

IOCFG19

RW

32

0x0000 6000

0x0000 004C

0x4008 104C

IOCFG20

RW

32

0x0000 6000

0x0000 0050

0x4008 1050

IOCFG21

RW

32

0x0000 6000

0x0000 0054

0x4008 1054

IOCFG22

RW

32

0x0000 6000

0x0000 0058

0x4008 1058

IOCFG23

RW

32

0x0000 6000

0x0000 005C

0x4008 105C

IOCFG24

RW

32

0x0000 6000

0x0000 0060

0x4008 1060

IOCFG25

RW

32

0x0000 6000

0x0000 0064

0x4008 1064

IOCFG26

RW

32

0x0000 6000

0x0000 0068

0x4008 1068

IOCFG27

RW

32

0x0000 6000

0x0000 006C

0x4008 106C

IOCFG28

RW

32

0x0000 6000

0x0000 0070

0x4008 1070

IOCFG29

RW

32

0x0000 6000

0x0000 0074

0x4008 1074

IOCFG30

RW

32

0x0000 6000

0x0000 0078

0x4008 1078

IOCFG31

RW

32

0x0000 6000

0x0000 007C

0x4008 107C

TOP:IOC Register Descriptions

TOP:IOC:IOCFG0

Address Offset 0x0000 0000
Physical Address 0x4008 1000 Instance 0x4008 1000
Description Configuration of DIO0
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / outut
0x7 OPENSRC_INV Open Source
Inverted input/output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO0
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG1

Address Offset 0x0000 0004
Physical Address 0x4008 1004 Instance 0x4008 1004
Description Configuration of DIO1
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO1
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG2

Address Offset 0x0000 0008
Physical Address 0x4008 1008 Instance 0x4008 1008
Description Configuration of DIO2
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO2
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG3

Address Offset 0x0000 000C
Physical Address 0x4008 100C Instance 0x4008 100C
Description Configuration of DIO3
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO3
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG4

Address Offset 0x0000 0010
Physical Address 0x4008 1010 Instance 0x4008 1010
Description Configuration of DIO4
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO4
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG5

Address Offset 0x0000 0014
Physical Address 0x4008 1014 Instance 0x4008 1014
Description Configuration of DIO5
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO5
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG6

Address Offset 0x0000 0018
Physical Address 0x4008 1018 Instance 0x4008 1018
Description Configuration of DIO6
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO6
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG7

Address Offset 0x0000 001C
Physical Address 0x4008 101C Instance 0x4008 101C
Description Configuration of DIO7
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO7
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG8

Address Offset 0x0000 0020
Physical Address 0x4008 1020 Instance 0x4008 1020
Description Configuration of DIO8
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO8
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG9

Address Offset 0x0000 0024
Physical Address 0x4008 1024 Instance 0x4008 1024
Description Configuration of DIO9
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO9
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG10

Address Offset 0x0000 0028
Physical Address 0x4008 1028 Instance 0x4008 1028
Description Configuration of DIO10
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO10
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG11

Address Offset 0x0000 002C
Physical Address 0x4008 102C Instance 0x4008 102C
Description Configuration of DIO11
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO11
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG12

Address Offset 0x0000 0030
Physical Address 0x4008 1030 Instance 0x4008 1030
Description Configuration of DIO12
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO12
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG13

Address Offset 0x0000 0034
Physical Address 0x4008 1034 Instance 0x4008 1034
Description Configuration of DIO13
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO13
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG14

Address Offset 0x0000 0038
Physical Address 0x4008 1038 Instance 0x4008 1038
Description Configuration of DIO14
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO14
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG15

Address Offset 0x0000 003C
Physical Address 0x4008 103C Instance 0x4008 103C
Description Configuration of DIO15
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO15
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG16

Address Offset 0x0000 0040
Physical Address 0x4008 1040 Instance 0x4008 1040
Description Configuration of DIO16
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b01
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO16
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG17

Address Offset 0x0000 0044
Physical Address 0x4008 1044 Instance 0x4008 1044
Description Configuration of DIO17
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b10
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO17
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG18

Address Offset 0x0000 0048
Physical Address 0x4008 1048 Instance 0x4008 1048
Description Configuration of DIO18
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO18
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG19

Address Offset 0x0000 004C
Physical Address 0x4008 104C Instance 0x4008 104C
Description Configuration of DIO19
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO19
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG20

Address Offset 0x0000 0050
Physical Address 0x4008 1050 Instance 0x4008 1050
Description Configuration of DIO20
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO20
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG21

Address Offset 0x0000 0054
Physical Address 0x4008 1054 Instance 0x4008 1054
Description Configuration of DIO21
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO21
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG22

Address Offset 0x0000 0058
Physical Address 0x4008 1058 Instance 0x4008 1058
Description Configuration of DIO22
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO22
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG23

Address Offset 0x0000 005C
Physical Address 0x4008 105C Instance 0x4008 105C
Description Configuration of DIO23
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO23
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG24

Address Offset 0x0000 0060
Physical Address 0x4008 1060 Instance 0x4008 1060
Description Configuration of DIO24
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO24
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG25

Address Offset 0x0000 0064
Physical Address 0x4008 1064 Instance 0x4008 1064
Description Configuration of DIO25
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO25
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG26

Address Offset 0x0000 0068
Physical Address 0x4008 1068 Instance 0x4008 1068
Description Configuration of DIO26
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO26
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG27

Address Offset 0x0000 006C
Physical Address 0x4008 106C Instance 0x4008 106C
Description Configuration of DIO27
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO27
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG28

Address Offset 0x0000 0070
Physical Address 0x4008 1070 Instance 0x4008 1070
Description Configuration of DIO28
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO28
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG29

Address Offset 0x0000 0074
Physical Address 0x4008 1074 Instance 0x4008 1074
Description Configuration of DIO29
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO29
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG30

Address Offset 0x0000 0078
Physical Address 0x4008 1078 Instance 0x4008 1078
Description Configuration of DIO30
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO30
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000

TOP:IOC:IOCFG31

Address Offset 0x0000 007C
Physical Address 0x4008 107C Instance 0x4008 107C
Description Configuration of DIO31
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 HYST_EN 0: Input hysteresis disable
1: Input hysteresis enable		 RW 0
29 IE 0: Input disabled
1: Input enabled

Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored.		 RW 0
28:27 WU_CFG If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08:

00: No wake-up
01: No wake-up
10: Wakes up from shutdown if this pad is going low.
11: Wakes up from shutdown if this pad is going high.

If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not.

00, 01: Wakeup disabled
10, 11: Wakeup enabled

Polarity is controlled from AON registers.

Note:When the MSB is set, the IOC will deactivate the output enable for the DIO.		 RW 0b00
26:24 IOMODE IO Mode
Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08
AUX has its own open_source/drain configuration.

0x2: Reserved. Undefined behavior.
0x3: Reserved. Undefined behavior.
Value ENUM Name Description
0x0 NORMAL Normal input / output
0x1 INV Inverted input / ouput
0x4 OPENDR Open Drain,
Normal input / output
0x5 OPENDR_INV Open Drain
Inverted input / output
0x6 OPENSRC Open Source
Normal input / output
0x7 OPENSRC_INV Open Source
Inverted input / output
RW 0b000
23 IOEV_AON_PROG2_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG2 event
1: Input edge detection asserts AON_PROG2 event		 RW 0
22 IOEV_AON_PROG1_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG1 event
1: Input edge detection asserts AON_PROG1 event		 RW 0
21 IOEV_AON_PROG0_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert AON_PROG0 event
1: Input edge detection asserts AON_PROG0 event		 RW 0
20:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00
18 EDGE_IRQ_EN 0: No interrupt generation
1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled)		 RW 0
17:16 EDGE_DET Enable generation of edge detection events on this IO
Value ENUM Name Description
0x0 NONE No edge detection
0x1 NEG Negative edge detection
0x2 POS Positive edge detection
0x3 BOTH Positive and negative edge detection
RW 0b00
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:13 PULL_CTL Pull control
Value ENUM Name Description
0x1 DWN Pull down
0x2 UP Pull up
0x3 DIS No pull
RW 0b11
12 SLEW_RED 0: Normal slew rate
1: Enables reduced slew rate in output driver.		 RW 0
11:10 IOCURR Selects IO current mode of this IO.
Value ENUM Name Description
0x0 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO
0x1 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO
0x2 4_8MA Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO
RW 0b00
9:8 IOSTR Select source for drive strength control of this IO.
This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR
Value ENUM Name Description
0x0 AUTO Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS)
0x1 MIN Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values)
0x2 MED Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values)
0x3 MAX Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values)
RW 0b00
7 IOEV_RTC_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert RTC event
1: Input edge detection asserts RTC event		 RW 0
6 IOEV_MCU_WU_EN Event asserted by this IO when edge detection is enabled

0: Input edge detection does not assert MCU_WU event
1: Input edge detection asserts MCU_WU event		 RW 0
5:0 PORT_ID Selects usage for DIO31
Value ENUM Name Description
0x0 GPIO General Purpose IO
0x7 AON_CLK32K AON 32 KHz clock (SCLK_LF)
0x8 AUX_IO AUX IO
0x9 SSI0_RX SSI0 RX
0xA SSI0_TX SSI0 TX
0xB SSI0_FSS SSI0 FSS
0xC SSI0_CLK SSI0 CLK
0xD I2C_MSSDA I2C Data
0xE I2C_MSSCL I2C Clock
0xF UART0_RX UART0 RX
0x10 UART0_TX UART0 TX
0x11 UART0_CTS UART0 CTS
0x12 UART0_RTS UART0 RTS
0x13 UART1_RX UART1 RX
0x14 UART1_TX UART1 TX
0x15 UART1_CTS UART1 CTS
0x16 UART1_RTS UART1 RTS
0x17 PORT_EVENT0 PORT EVENT 0
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x18 PORT_EVENT1 PORT EVENT 1
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x19 PORT_EVENT2 PORT EVENT 2
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1A PORT_EVENT3 PORT EVENT 3
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1B PORT_EVENT4 PORT EVENT 4
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1C PORT_EVENT5 PORT EVENT 5
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1D PORT_EVENT6 PORT EVENT 6
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x1E PORT_EVENT7 PORT EVENT 7
Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on
0x20 CPU_SWV CPU SWV
0x21 SSI1_RX SSI1 RX
0x22 SSI1_TX SSI1 TX
0x23 SSI1_FSS SSI1 FSS
0x24 SSI1_CLK SSI1 CLK
0x25 I2S_AD0 I2S Data 0
0x26 I2S_AD1 I2S Data 1
0x27 I2S_WCLK I2S WCLK
0x28 I2S_BCLK I2S BCLK
0x29 I2S_MCLK I2S MCLK
0x2E RFC_TRC RF Core Trace
0x2F RFC_GPO0 RF Core Data Out 0
0x30 RFC_GPO1 RF Core Data Out 1
0x31 RFC_GPO2 RF Core Data Out 2
0x32 RFC_GPO3 RF Core Data Out 3
0x33 RFC_GPI0 RF Core Data In 0
0x34 RFC_GPI1 RF Core Data In 1
0x35 RFC_SMI_DL_OUT RF Core SMI Data Link Out
0x36 RFC_SMI_DL_IN RF Core SMI Data Link In
0x37 RFC_SMI_CL_OUT RF Core SMI Command Link Out
0x38 RFC_SMI_CL_IN RF Core SMI Command Link In
RW 0b00 0000


© 2015 - 2016. Texas Instruments | All Rights Reserved