CC26xx Driver Library
Macros | Typedefs | Functions | Variables
flash.c File Reference
#include "../inc/hw_types.h"
#include "../inc/hw_ccfg.h"
#include "flash.h"
#include "rom.h"
#include "chipinfo.h"

Macros

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG
 
#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0
 
#define CCFG_SIZE_SECURITY   0x00000014
 
#define CCFG_SIZE_SECT_PROT   0x00000004
 

Typedefs

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)
 
typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)
 

Functions

static void SetReadMode (void)
 
void FlashPowerModeSet (uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)
 Set power mode. More...
 
uint32_t FlashPowerModeGet (void)
 Get current configured power mode. More...
 
void FlashProtectionSet (uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)
 Set sector protection. More...
 
uint32_t FlashProtectionGet (uint32_t ui32SectorAddress)
 Get sector protection. More...
 
uint32_t FlashProtectionSave (uint32_t ui32SectorAddress)
 Save sector protection to make it permanent. More...
 
uint32_t FlashSectorErase (uint32_t ui32SectorAddress)
 Erase a flash sector. More...
 
uint32_t FlashProgram (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 Programs unprotected flash sectors in the main bank. More...
 
bool FlashEfuseReadRow (uint32_t *pui32EfuseData, uint32_t ui32RowAddress)
 Reads efuse data from specified row. More...
 
void FlashDisableSectorsForWrite (void)
 Disables all sectors for erase and programming on the active bank. More...
 
uint32_t MemBusWrkAroundHapiProgramFlash (uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
 
uint32_t MemBusWrkAroundHapiEraseSector (uint32_t ui32Address)
 

Variables

const uint8_t g_pui8CcfgDefaultSec []
 

Macro Definition Documentation

#define CCFG_OFFSET_SECT_PROT   CCFG_O_CCFG_PROT_31_0

Referenced by FlashProtectionSave().

#define CCFG_OFFSET_SECURITY   CCFG_O_BL_CONFIG
#define CCFG_SIZE_SECT_PROT   0x00000004

Referenced by FlashProtectionSave().

#define CCFG_SIZE_SECURITY   0x00000014

Typedef Documentation

typedef uint32_t(* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t)
typedef uint32_t(* FlashSectorErasePointer_t) (uint32_t)

Function Documentation

uint32_t MemBusWrkAroundHapiEraseSector ( uint32_t  ui32Address)
657 {
658  uint32_t ui32ErrorReturn;
659 
660  FlashSectorErasePointer_t FuncPointer;
661  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4));
662 
663  // Call ROM function
664  FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr);
665  ui32ErrorReturn = FuncPointer(ui32Address);
666 
667  // Enable standby in flash bank since ROM function might have disabled it
668  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
669 
670  // Return status of operation.
671  return(ui32ErrorReturn);
672 }
FlashSectorErasePointer_t
uint32_t(* FlashSectorErasePointer_t)(uint32_t)
Definition: flash.c:99
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:59
uint32_t MemBusWrkAroundHapiProgramFlash ( uint8_t *  pui8DataBuffer,
uint32_t  ui32Address,
uint32_t  ui32Count 
)
634 {
635  uint32_t ui32ErrorReturn;
636  FlashPrgPointer_t FuncPointer;
637  uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4));
638 
639  // Call ROM function
640  FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr);
641  ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
642 
643  // Enable standby in flash bank since ROM function might have disabled it
644  HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
645 
646  // Return status of operation.
647  return(ui32ErrorReturn);
648 }
ROM_HAPI_TABLE_ADDR
#define ROM_HAPI_TABLE_ADDR
Definition: rom.h:59
FlashPrgPointer_t
uint32_t(* FlashPrgPointer_t)(uint8_t *, uint32_t, uint32_t)
Definition: flash.c:97
static void SetReadMode ( void  )
static

Referenced by FlashDisableSectorsForWrite().

485 {
486  uint32_t ui32TrimValue;
487  uint32_t ui32Value;
488 
489  // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
490  // VIN_AT_X and VIN_BY_PASS for read mode
491  if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
492  AON_PMCTL_PWRCTL_EXT_REG_MODE)
493  {
494  // Select trim values for external regulator mode:
495  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
496  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
497  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
498  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
499 
500  ui32TrimValue =
501  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
502 
503  ui32Value = ((ui32TrimValue &
504  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
505  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
506  FLASH_CFG_STANDBY_MODE_SEL_S;
507 
508  ui32Value |= ((ui32TrimValue &
509  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
510  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
511  FLASH_CFG_STANDBY_PW_SEL_S;
512 
513  // Configure DIS_STANDBY (OTP offset 0x308 bit 4).
514  // Configure DIS_IDLE (OTP offset 0x308 bit 3).
515  ui32Value |= ((ui32TrimValue &
516  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
517  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
518  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
519  FLASH_CFG_DIS_IDLE_S;
520 
521  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
522  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
523  FLASH_CFG_STANDBY_PW_SEL_M |
524  FLASH_CFG_DIS_STANDBY_M |
525  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
526 
527  // Check if sample and hold functionality is disabled.
528  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
529  {
530  // Wait for disabled sample and hold functionality to be stable.
531  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
532  {
533  }
534  }
535 
536  // Configure VIN_AT_X (OTP offset 0x308 bits 2:0)
537  ui32Value = ((ui32TrimValue &
538  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
539  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
540  FLASH_FSEQPMP_VIN_AT_X_S;
541 
542  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
543  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
544  // VIN_BY_PASS should be 1
545  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
546  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
547  {
548  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
549  }
550 
551  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
552  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
553  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
554  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
555  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
556  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
557  }
558  else
559  {
560  // Select trim values for internal regulator mode:
561  // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
562  // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
563  // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
564  HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
565 
566  ui32TrimValue =
567  HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
568 
569  ui32Value = ((ui32TrimValue &
570  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
571  FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
572  FLASH_CFG_STANDBY_MODE_SEL_S;
573 
574  ui32Value |= ((ui32TrimValue &
575  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
576  FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
577  FLASH_CFG_STANDBY_PW_SEL_S;
578 
579  // Configure DIS_STANDBY (OTP offset 0x308 bit 12).
580  // Configure DIS_IDLE (OTP offset 0x308 bit 11).
581  ui32Value |= ((ui32TrimValue &
582  (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
583  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
584  FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
585  FLASH_CFG_DIS_IDLE_S;
586 
587  HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
588  ~(FLASH_CFG_STANDBY_MODE_SEL_M |
589  FLASH_CFG_STANDBY_PW_SEL_M |
590  FLASH_CFG_DIS_STANDBY_M |
591  FLASH_CFG_DIS_IDLE_M)) | ui32Value;
592 
593  // Check if sample and hold functionality is disabled.
594  if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
595  {
596  // Wait for disabled sample and hold functionality to be stable.
597  while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
598  {
599  }
600  }
601 
602  // Configure VIN_AT_X (OTP offset 0x308 bits 10:8)
603  ui32Value = (((ui32TrimValue &
604  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
605  FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
606  FLASH_FSEQPMP_VIN_AT_X_S);
607 
608  // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
609  // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
610  // VIN_BY_PASS should be 1
611  if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
612  FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
613  {
614  ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
615  }
616 
617  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
618  HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
619  (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
620  ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
621  FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
622  HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
623  }
624 }
FCFG1_OFFSET
#define FCFG1_OFFSET
Definition: flash.h:150

Variable Documentation

const uint8_t g_pui8CcfgDefaultSec[]
Initial value:
= {0xFF, 0xFF, 0xFF, 0xC5,
0xFF, 0xFF, 0xFF, 0xFF,
0xC5, 0xFF, 0xFF, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF,
0xC5, 0xC5, 0xC5, 0xFF
}