SPICC26XXDMA Hardware attributes. More...

#include <SPICC26XXDMA.h>

Data Fields
uint32_t	baseAddr

uint8_t	intNum

uint8_t	intPriority
	SPI CC26XXDMA Peripheral's interrupt priority. More...

uint32_t	swiPriority
	SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. More...

PowerCC26XX_Resource	powerMngrId

uint16_t	defaultTxBufValue

uint32_t	rxChannelBitMask

uint32_t	txChannelBitMask

PIN_Id	mosiPin

PIN_Id	misoPin

PIN_Id	clkPin

PIN_Id	csnPin

uint32_t	minDmaTransferSize

Detailed Description

SPICC26XXDMA Hardware attributes.

These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For CC26xxWare these definitions are found in:

inc/hw_memmap.h
inc/hw_ints.h
driverlib/udma.h

intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

const SPICC26XXDMA_HWAttrsV1 spiCC26XXDMAobjects[] = {
    {
        .baseAddr = SSI0_BASE,
        .intNum = INT_SPI0,
        .intPriority = ~0,
        .swiPriority = 0,
        .powerMngrId = PERIPH_SPI0,
        .defaultTxBufValue = 0,
        .rxChannelBitMask = UDMA_CHAN_SPI0_RX,
        .txChannelBitMask = UDMA_CHAN_SPI0_TX,
        .mosiPin = Board_SPI0_MISO,
        .misoPin = Board_SPI0_MOSI,
        .clkPin = Board_SPI0_CLK,
        .csnPin = Board_SPI0_CSN
    },
    {
        .baseAddr = SSI1_BASE,
        .intNum = INT_SPI1,
        .intPriority = ~0,
        .swiPriority = 0,
        .powerMngrId = PERIPH_SPI1,
        .defaultTxBufValue = 0,
        .rxChannelBitMask = UDMA_CHAN_SPI1_RX,
        .txChannelBitMask = UDMA_CHAN_SPI1_TX,
        .mosiPin = Board_SPI1_MISO,
        .misoPin = Board_SPI1_MOSI,
        .clkPin = Board_SPI1_CLK,
        .csnPin = Board_SPI1_CSN
    },
};

Field Documentation

§ baseAddr

uint32_t SPICC26XXDMA_HWAttrsV1::baseAddr

SPI Peripheral's base address

§ intNum

uint8_t SPICC26XXDMA_HWAttrsV1::intNum

SPI CC26XXDMA Peripheral's interrupt vector

§ intPriority

uint8_t SPICC26XXDMA_HWAttrsV1::intPriority

SPI CC26XXDMA Peripheral's interrupt priority.

The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5).

(7 << 5) will apply the lowest priority.

(1 << 5) will apply the highest priority.

Setting the priority to 0 is not supported by this driver.

HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

§ swiPriority

uint32_t SPICC26XXDMA_HWAttrsV1::swiPriority

SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file.

§ powerMngrId

PowerCC26XX_Resource SPICC26XXDMA_HWAttrsV1::powerMngrId

SPI Peripheral's power manager ID

§ defaultTxBufValue

uint16_t SPICC26XXDMA_HWAttrsV1::defaultTxBufValue

Default TX value if txBuf == NULL

§ rxChannelBitMask

uint32_t SPICC26XXDMA_HWAttrsV1::rxChannelBitMask

uDMA controlTable channel index

§ txChannelBitMask

uint32_t SPICC26XXDMA_HWAttrsV1::txChannelBitMask

uDMA controlTable channel index

§ mosiPin

PIN_Id SPICC26XXDMA_HWAttrsV1::mosiPin

SPI MOSI pin

§ misoPin

PIN_Id SPICC26XXDMA_HWAttrsV1::misoPin

SPI MISO pin

§ clkPin

PIN_Id SPICC26XXDMA_HWAttrsV1::clkPin

SPI CLK pin

§ csnPin

PIN_Id SPICC26XXDMA_HWAttrsV1::csnPin

SPI CSN pin

§ minDmaTransferSize

uint32_t SPICC26XXDMA_HWAttrsV1::minDmaTransferSize

Minimum transfer size for DMA based transfer

The documentation for this struct was generated from the following file:

SPICC26XXDMA.h

Data Fields