486 uint32_t ui32TrimValue;
491 if(HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL) &
492 AON_SYSCTL_PWRCTL_EXT_REG_MODE)
498 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
501 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
503 ui32Value = ((ui32TrimValue &
504 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
505 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
506 FLASH_CFG_STANDBY_MODE_SEL_S;
508 ui32Value |= ((ui32TrimValue &
509 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
510 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
511 FLASH_CFG_STANDBY_PW_SEL_S;
515 ui32Value |= ((ui32TrimValue &
516 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
517 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
518 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
519 FLASH_CFG_DIS_IDLE_S;
521 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
522 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
523 FLASH_CFG_STANDBY_PW_SEL_M |
524 FLASH_CFG_DIS_STANDBY_M |
525 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
528 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
531 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
537 ui32Value = ((ui32TrimValue &
538 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
539 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
540 FLASH_FSEQPMP_VIN_AT_X_S;
545 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
546 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
548 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
551 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
552 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
553 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
554 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
555 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
556 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
564 HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
567 HWREG(FLASH_CFG_BASE +
FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
569 ui32Value = ((ui32TrimValue &
570 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
571 FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
572 FLASH_CFG_STANDBY_MODE_SEL_S;
574 ui32Value |= ((ui32TrimValue &
575 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
576 FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
577 FLASH_CFG_STANDBY_PW_SEL_S;
581 ui32Value |= ((ui32TrimValue &
582 (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
583 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
584 FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
585 FLASH_CFG_DIS_IDLE_S;
587 HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
588 ~(FLASH_CFG_STANDBY_MODE_SEL_M |
589 FLASH_CFG_STANDBY_PW_SEL_M |
590 FLASH_CFG_DIS_STANDBY_M |
591 FLASH_CFG_DIS_IDLE_M)) | ui32Value;
594 if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
597 while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
603 ui32Value = (((ui32TrimValue &
604 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
605 FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
606 FLASH_FSEQPMP_VIN_AT_X_S);
611 if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
612 FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
614 ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
617 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
618 HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
619 (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
620 ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
621 FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
622 HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
#define FCFG1_OFFSET
Definition: flash.h:150