[prcm.h] Power Reset Clock Manager

Functions
void	PRCMInfClockConfigureSet (uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
	Configure the infrastructure clock. More...
uint32_t	PRCMInfClockConfigureGet (uint32_t ui32PowerMode)
	Use this function to get the infrastructure clock configuration. More...
static void	PRCMMcuUldoConfigure (uint32_t ui32Enable)
	Assert or de-assert a request for the uLDO. More...
static void	PRCMGPTimerClockDivisionSet (uint32_t clkDiv)
	Setup the clock division factor for the GP-Timer domain. More...
static uint32_t	PRCMGPTimerClockDivisionGet (void)
	Get the clock division factor for the GP-Timer domain. More...
static void	PRCMAudioClockEnable (void)
	Enable the audio clock generation. More...
static void	PRCMAudioClockDisable (void)
	Disable the audio clock generation. More...
void	PRCMAudioClockConfigSet (uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
	Configure the audio clock generation. More...
void	PRCMAudioClockConfigSetOverride (uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)
	Configure the audio clock generation with manual setting of clock divider. More...
static void	PRCMLoadSet (void)
	Use this function to synchronize the load settings. More...
static bool	PRCMLoadGet (void)
	Check if any of the load sensitive register has been updated. More...
static void	PRCMDomainEnable (uint32_t ui32Domains)
	Enable clock domains in the MCU voltage domain. More...
static void	PRCMDomainDisable (uint32_t ui32Domains)
	Disable clock domains in the MCU voltage domain. More...
void	PRCMPowerDomainOn (uint32_t ui32Domains)
	Turn power on in power domains in the MCU domain. More...
void	PRCMPowerDomainOff (uint32_t ui32Domains)
	Turn off a specific power domain. More...
static void	PRCMRfPowerDownWhenIdle (void)
	Configure RF core to power down when idle. More...
void	PRCMPeripheralRunEnable (uint32_t ui32Peripheral)
	Enables a peripheral in Run mode. More...
void	PRCMPeripheralRunDisable (uint32_t ui32Peripheral)
	Disables a peripheral in Run mode. More...
void	PRCMPeripheralSleepEnable (uint32_t ui32Peripheral)
	Enables a peripheral in sleep mode. More...
void	PRCMPeripheralSleepDisable (uint32_t ui32Peripheral)
	Disables a peripheral in sleep mode. More...
void	PRCMPeripheralDeepSleepEnable (uint32_t ui32Peripheral)
	Enables a peripheral in deep-sleep mode. More...
void	PRCMPeripheralDeepSleepDisable (uint32_t ui32Peripheral)
	Disables a peripheral in deep-sleep mode. More...
uint32_t	PRCMPowerDomainStatus (uint32_t ui32Domains)
	Get the status for a specific power domain. More...
static bool	PRCMRfReady (void)
	Return the access status of the RF Core. More...
static void	PRCMSleep (void)
	Put the processor into sleep mode. More...
void	PRCMDeepSleep (void)
	Put the processor into deep-sleep mode. More...
static void	PRCMCacheRetentionEnable (void)
	Enable CACHE RAM retention. More...
static void	PRCMCacheRetentionDisable (void)
	Disable CACHE RAM retention. More...

Detailed Description

Function Documentation

void PRCMAudioClockConfigSet	(	uint32_t	ui32ClkConfig,
		uint32_t	ui32SampleRate
	)

Configure the audio clock generation.

Use this function to set the sample rate when using internal audio clock generation for the I2S module.

Note

While other clocks are possible, the stability of the four sample rates defined here are only guaranteed if the clock input to the I2S module is 48MHz.

Parameters

ui32ClkConfig	is the audio clock configuration. The parameter is a bitwise OR'ed value consisting of: Phase PRCM_WCLK_SINGLE_PHASE PRCM_WCLK_DUAL_PHASE Clock polarity PRCM_WCLK_NEG_EDGE PRCM_WCLK_POS_EDGE
ui32SampleRate	is the desired audio clock sample rate. The supported sample rate configurations are: I2S_SAMPLE_RATE_16K I2S_SAMPLE_RATE_24K I2S_SAMPLE_RATE_32K I2S_SAMPLE_RATE_48K

Returns

None

See also

PRCMAudioClockConfigSetOverride()

{
    uint32_t ui32Reg;
    uint32_t ui32MstDiv;
    uint32_t ui32BitDiv;
    uint32_t ui32WordDiv;

    // Check the arguments.
    ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
    ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
           (ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
           (ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
           (ui32SampleRate == I2S_SAMPLE_RATE_48K));

    ui32MstDiv = 0;
    ui32BitDiv = 0;
    ui32WordDiv = 0;

    // Make sure the audio clock generation is disabled before reconfiguring.
    PRCMAudioClockDisable();

    // Define the clock division factors for the audio interface.
    switch(ui32SampleRate)
    {
    case I2S_SAMPLE_RATE_16K :
        ui32MstDiv = 6;
        ui32BitDiv = 60;
        ui32WordDiv = 25;
        break;
    case I2S_SAMPLE_RATE_24K :
        ui32MstDiv = 4;
        ui32BitDiv = 40;
        ui32WordDiv = 25;
        break;
    case I2S_SAMPLE_RATE_32K :
        ui32MstDiv = 3;
        ui32BitDiv = 30;
        ui32WordDiv = 25;
        break;
    case I2S_SAMPLE_RATE_48K :
        ui32MstDiv = 2;
        ui32BitDiv = 20;
        ui32WordDiv = 25;
        break;
    }

    // Make sure to compensate the Frame clock division factor if using single
    // phase format.
    if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
    {
        ui32WordDiv -= 1;
    }

    // Write the clock division factors.
    HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
    HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
    HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;

    // Configure the Word clock format and polarity.
    ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
              PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
    HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}

Here is the call graph for this function:

void PRCMAudioClockConfigSetOverride	(	uint32_t	ui32ClkConfig,
		uint32_t	ui32MstDiv,
		uint32_t	ui32BitDiv,
		uint32_t	ui32WordDiv
	)

Configure the audio clock generation with manual setting of clock divider.

Use this function to set the audio clock divider values manually.

Note

See hardware documentation before setting audio clock dividers manually.

Parameters

ui32ClkConfig	is the audio clock configuration. The parameter is a bitwise OR'ed value consisting of: Phase PRCM_WCLK_SINGLE_PHASE PRCM_WCLK_DUAL_PHASE Clock polarity PRCM_WCLK_NEG_EDGE PRCM_WCLK_POS_EDGE
ui32MstDiv	is the desired master clock divider.
ui32WordDiv	is the desired word clock divider.
ui32BitDiv	is the desired bit clock divider.

Returns

None

See also

PRCMAudioClockConfigSet()

{
    uint32_t ui32Reg;

    // Check the arguments.
    ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));

    // Make sure the audio clock generation is disabled before reconfiguring.
    PRCMAudioClockDisable();

    // Make sure to compensate the Frame clock division factor if using single
    // phase format.
    if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
    {
        ui32WordDiv -= 1;
    }

    // Write the clock division factors.
    HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
    HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
    HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;

    // Configure the Word clock format and polarity.
    ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
              PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
    HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}

Here is the call graph for this function:

static void PRCMAudioClockDisable ( void  )

inlinestatic

Disable the audio clock generation.

Use this function to disable the audio clock generation.

Returns

None

Referenced by PRCMAudioClockConfigSet(), and PRCMAudioClockConfigSetOverride().

{
    // Disable the audio clock generation
    HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0;
}

static void PRCMAudioClockEnable ( void  )

inlinestatic

Enable the audio clock generation.

Use this function to enable the audio clock generation.

Returns

None

{
    // Enable the audio clock generation.
    HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1;
}

static void PRCMCacheRetentionDisable ( void  )

inlinestatic

Disable CACHE RAM retention.

Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM

Returns

None

Referenced by SysCtrlStandby().

{
   HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M;
}

static void PRCMCacheRetentionEnable ( void  )

inlinestatic

Enable CACHE RAM retention.

Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM

Returns

None

Referenced by SysCtrlIdle().

{
   HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M;
}

void PRCMDeepSleep

(

void

)

Put the processor into deep-sleep mode.

This function places the processor into deep-sleep mode; it does not return until the processor returns to run mode. The peripherals that are enabled via PRCMPeripheralDeepSleepEnable() continue to operate and can wake up the processor.

Returns

None

See also

PRCMPeripheralDeepSleepEnable()

Referenced by SysCtrlIdle(), and SysCtrlStandby().

{
    // Enable deep-sleep.
    HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;

    // Wait for an interrupt.
    CPUwfi();

    // Disable deep-sleep so that a future sleep will work correctly.
    HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
}

Here is the call graph for this function:

static void PRCMDomainDisable ( uint32_t  ui32Domains )

inlinestatic

Disable clock domains in the MCU voltage domain.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Clocks will only be running if the domain is powered.

Parameters

ui32Domains

is a bit mask containing the clock domains to disable. The independent clock domains inside the MCU voltage domain are: PRCM_DOMAIN_RFCORE PRCM_DOMAIN_VIMS

Returns

None

See also

PRCMDomainEnable()

{
    // Check the arguments.
    ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
           (ui32Domains & PRCM_DOMAIN_VIMS));

    // Disable the power domains.
    if(ui32Domains & PRCM_DOMAIN_RFCORE)
    {
        HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0;
    }
    if(ui32Domains & PRCM_DOMAIN_VIMS)
    {
        HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0;
    }
}

static void PRCMDomainEnable ( uint32_t  ui32Domains )

inlinestatic

Enable clock domains in the MCU voltage domain.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Clocks will only be running if the domain is powered.

Parameters

ui32Domains

is a bit mask containing the clock domains to enable. The independent clock domains inside the MCU voltage domain which can be configured are: PRCM_DOMAIN_RFCORE PRCM_DOMAIN_VIMS

Returns

None

{
    // Check the arguments.
    ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
           (ui32Domains & PRCM_DOMAIN_VIMS));

    // Enable the clock domain(s).
    if(ui32Domains & PRCM_DOMAIN_RFCORE)
    {
        HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN;
    }
    if(ui32Domains & PRCM_DOMAIN_VIMS)
    {
        HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M;
    }
}

static uint32_t PRCMGPTimerClockDivisionGet ( void  )

inlinestatic

Get the clock division factor for the GP-Timer domain.

Use this function to get the clock division factor set for the GP-Timer.

Returns

Returns one of the following values:

• PRCM_CLOCK_DIV_1
• PRCM_CLOCK_DIV_2
• PRCM_CLOCK_DIV_4
• PRCM_CLOCK_DIV_8
• PRCM_CLOCK_DIV_16
• PRCM_CLOCK_DIV_32
• PRCM_CLOCK_DIV_64
• PRCM_CLOCK_DIV_128
• PRCM_CLOCK_DIV_256

See also

PRCMGPTimerClockDivisionSet()

{
    return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ));
}

static void PRCMGPTimerClockDivisionSet ( uint32_t  clkDiv )

inlinestatic

Setup the clock division factor for the GP-Timer domain.

Use this function to set up the clock division factor on the GP-Timer.

The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when it is slower than PRCM_GPTCLKDIV_RATIO setting. When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. Note that the register will contain the written content even though the setting is faster than PRCM_GPTCLKDIV_RATIO setting.

Note

For change to take effect, PRCMLoadSet() needs to be called

Parameters

clkDiv

is the division factor to set. The argument must be only one of the following values: PRCM_CLOCK_DIV_1 PRCM_CLOCK_DIV_2 PRCM_CLOCK_DIV_4 PRCM_CLOCK_DIV_8 PRCM_CLOCK_DIV_16 PRCM_CLOCK_DIV_32 PRCM_CLOCK_DIV_64 PRCM_CLOCK_DIV_128 PRCM_CLOCK_DIV_256

Returns

None

See also

PRCMGPTimerClockDivisionGet()

{
    ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 );

    HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv;
}

uint32_t PRCMInfClockConfigureGet

(

uint32_t

ui32PowerMode

)

Use this function to get the infrastructure clock configuration.

Parameters

ui32PowerMode

determines which System CPU power mode to return the infrastructure clock division ratio for. The three allowed power modes are: PRCM_RUN_MODE PRCM_SLEEP_MODE PRCM_DEEP_SLEEP_MODE

Returns

Returns the infrastructure clock division factor for the specified power mode.

• PRCM_CLOCK_DIV_1
• PRCM_CLOCK_DIV_2
• PRCM_CLOCK_DIV_8
• PRCM_CLOCK_DIV_32

See also

PRCMInfClockConfigureSet().

{
    uint32_t ui32ClkDiv;
    uint32_t ui32Divisor;

    // Check the arguments.
    ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
           (ui32PowerMode == PRCM_SLEEP_MODE) ||
           (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));

    ui32ClkDiv = 0;
    ui32Divisor = 0;

    // Determine the correct power mode.
    if(ui32PowerMode == PRCM_RUN_MODE)
    {
        ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR);
    }
    else if(ui32PowerMode == PRCM_SLEEP_MODE)
    {
        ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS);
    }
    else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
    {
        ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS);
    }

    // Find the correct division factor.
    if(ui32ClkDiv == 0x0)
    {
        ui32Divisor = PRCM_CLOCK_DIV_1;
    }
    else if(ui32ClkDiv == 0x1)
    {
        ui32Divisor = PRCM_CLOCK_DIV_2;
    }
    else if(ui32ClkDiv == 0x2)
    {
        ui32Divisor = PRCM_CLOCK_DIV_8;
    }
    else if(ui32ClkDiv == 0x3)
    {
        ui32Divisor = PRCM_CLOCK_DIV_32;
    }

    // Return the clock division factor.
    return ui32Divisor;
}

void PRCMInfClockConfigureSet	(	uint32_t	ui32ClkDiv,
		uint32_t	ui32PowerMode
	)

Configure the infrastructure clock.

Each System CPU power mode has its own infrastructure clock division factor. This function can be used for setting up the division factor for the infrastructure clock in the available power modes for the System CPU. The infrastructure clock is used for all internal logic in the PRCM, and is always running as long as power is on in the MCU voltage domain. This can be enabled and disabled from the AON Wake Up Controller.

Note

If source clock is 48 MHz, minimum clock divider is PRCM_CLOCK_DIV_2.

Parameters

ui32ClkDiv	determines the division ratio for the infrastructure clock when the device is in the specified mode. Allowed division factors for all three System CPU power modes are: PRCM_CLOCK_DIV_1 PRCM_CLOCK_DIV_2 PRCM_CLOCK_DIV_8 PRCM_CLOCK_DIV_32
ui32PowerMode	determines the System CPU operation mode for which to modify the clock division factor. The three allowed power modes are: PRCM_RUN_MODE PRCM_SLEEP_MODE PRCM_DEEP_SLEEP_MODE

Returns

None

{
    uint32_t ui32Divisor;

    // Check the arguments.
    ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
           (ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
           (ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
           (ui32ClkDiv == PRCM_CLOCK_DIV_32));
    ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
           (ui32PowerMode == PRCM_SLEEP_MODE) ||
           (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));

    ui32Divisor = 0;

    // Find the correct division factor.
    if(ui32ClkDiv == PRCM_CLOCK_DIV_1)
    {
        ui32Divisor = 0x0;
    }
    else if(ui32ClkDiv == PRCM_CLOCK_DIV_2)
    {
        ui32Divisor = 0x1;
    }
    else if(ui32ClkDiv == PRCM_CLOCK_DIV_8)
    {
        ui32Divisor = 0x2;
    }
    else if(ui32ClkDiv == PRCM_CLOCK_DIV_32)
    {
        ui32Divisor = 0x3;
    }

    // Determine the correct power mode set the division factor accordingly.
    if(ui32PowerMode == PRCM_RUN_MODE)
    {
        HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor;
    }
    else if(ui32PowerMode == PRCM_SLEEP_MODE)
    {
        HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor;
    }
    else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
    {
        HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor;
    }
}

static bool PRCMLoadGet ( void  )

inlinestatic

Check if any of the load sensitive register has been updated.

Returns

Returns status of the load sensitive register:

• true : No registers have changed since the last load.
• false : Any register has changed.

See also

PRCMLoadSet()

Referenced by SysCtrlStandby().

{
    // Return the load status.
    return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ?
            true : false);
}

static void PRCMLoadSet ( void  )

inlinestatic

Use this function to synchronize the load settings.

Most of the clock settings in the PRCM module should be updated synchronously. This is ensured by the implementation of a load registers that, when written to, will let the previous written update values for all the relevant registers propagate through to hardware.

The functions that require a synchronization of the clock settings are:

• PRCMAudioClockConfigSet()
• PRCMAudioClockConfigSetOverride()
• PRCMAudioClockDisable()
• PRCMDomainEnable()
• PRCMDomainDisable()
• PRCMPeripheralRunEnable()
• PRCMPeripheralRunDisable()
• PRCMPeripheralSleepEnable()
• PRCMPeripheralSleepDisable()
• PRCMPeripheralDeepSleepEnable()
• PRCMPeripheralDeepSleepDisable()

Returns

None

See also

PRCMLoadGet()

Referenced by SysCtrlStandby().

{
    // Enable the update of all load related registers.
    HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD;
}

static void PRCMMcuUldoConfigure ( uint32_t  ui32Enable )

inlinestatic

Assert or de-assert a request for the uLDO.

Use this function to request to switch to the micro Low Voltage Dropout regulator (uLDO). The uLDO has a much lower capacity for supplying power to the system. It is therefore imperative and solely the programmers responsibility to ensure that a sufficient amount of peripheral modules have been turned of before requesting a switch to the uLDO.

Note

Asserting this bit has no effect until:

1. FLASH has accepted to be powered down
2. Deepsleep must be asserted

Parameters

ui32Enable

0 : Disable uLDO request 1 : Enable uLDO request

Returns

None

See also

PRCMDeepSleep()

Referenced by PowerCtrlSourceSet(), and SysCtrlStandby().

{
    // Enable or disable the uLDO request signal.
    HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable;
}

void PRCMPeripheralDeepSleepDisable

(

uint32_t

ui32Peripheral

)

Disables a peripheral in deep-sleep mode.

This function causes a peripheral to stop operating when the processor goes into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps to lower the current draw of the device, and can keep peripherals that require a particular clock frequency from operating when the clock changes as a result of entering deep-sleep mode. If enabled (via PRCMPeripheralRunEnable()), the peripheral will automatically resume operation when the processor leaves deep-sleep mode, maintaining its entire state from before deep-sleep mode was entered.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Parameters

ui32Peripheral

is the peripheral to disable in deep-sleep mode. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

Referenced by SysCtrlStandby().

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Disable this peripheral in Deep Sleep mode.
    HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
        ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPeripheralDeepSleepEnable

(

uint32_t

ui32Peripheral

)

Enables a peripheral in deep-sleep mode.

This function allows a peripheral to continue operating when the processor goes into deep-sleep mode. Since the clocking configuration of the device may change, not all peripherals can safely continue operating while the processor is in sleep mode. This in turn depends on the chosen power mode. It is the responsibility of the caller to make sensible choices.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Parameters

ui32Peripheral

is the peripheral to enable in deep-sleep mode. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Enable this peripheral in deep-sleep mode.
    HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
        PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPeripheralRunDisable

(

uint32_t

ui32Peripheral

)

Disables a peripheral in Run mode.

Peripherals are disabled with this function. Once disabled, they will not operate or respond to register reads/writes.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

The actual disabling of the peripheral may be delayed until some time after this function returns. Care should be taken by the user to ensure that the peripheral is not accessed in this interval as this might cause the system to hang.

Parameters

ui32Peripheral

is the peripheral to disable. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Disable module in Run Mode.
    HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
        ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPeripheralRunEnable

(

uint32_t

ui32Peripheral

)

Enables a peripheral in Run mode.

Peripherals are enabled with this function. At power-up, some peripherals are disabled; they must be enabled in order to operate or respond to register reads/writes.

Note

The actual enabling of the peripheral may be delayed until some time after this function returns. Care should be taken to ensure that the peripheral is not accessed until it is enabled. When enabling Timers always make sure that the division factor for the PERBUSCPUCLK is set. This will guarantee that the timers run at a continuous rate even if the SYSBUSCLK is gated.

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Parameters

ui32Peripheral

is the peripheral to enable. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Enable module in Run Mode.
    HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
        PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPeripheralSleepDisable

(

uint32_t

ui32Peripheral

)

Disables a peripheral in sleep mode.

This function causes a peripheral to stop operating when the processor goes into sleep mode. Disabling peripherals while in sleep mode helps to lower the current draw of the device. If enabled (via PRCMPeripheralRunEnable()), the peripheral will automatically resume operation when the processor leaves sleep mode, maintaining its entire state from before sleep mode was entered.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Parameters

ui32Peripheral

is the peripheral to disable in sleep mode. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Disable this peripheral in sleep mode
    HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
        ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPeripheralSleepEnable

(

uint32_t

ui32Peripheral

)

Enables a peripheral in sleep mode.

This function allows a peripheral to continue operating when the processor goes into sleep mode. Since the clocking configuration of the device does not change, any peripheral can safely continue operating while the processor is in sleep mode, and can therefore wake the processor from sleep mode.

Note

A call to this function will only setup the shadow registers in the MCU domain for the PRCM module. For the changes to propagate to the system controller in the AON domain a call to this function should always be followed by a call to PRCMLoadSet().

Parameters

ui32Peripheral

is the peripheral to enable in sleep mode. The parameter must be one of the following: PRCM_PERIPH_TIMER0 PRCM_PERIPH_TIMER1 PRCM_PERIPH_TIMER2 PRCM_PERIPH_TIMER3 PRCM_PERIPH_SSI0 PRCM_PERIPH_SSI1 PRCM_PERIPH_UART0 PRCM_PERIPH_UART1 PRCM_PERIPH_I2C0 PRCM_PERIPH_CRYPTO PRCM_PERIPH_TRNG PRCM_PERIPH_PKA PRCM_PERIPH_UDMA PRCM_PERIPH_GPIO PRCM_PERIPH_I2S

Returns

None

See also

PRCMLoadSet()

{
    // Check the arguments.
    ASSERT(PRCMPeripheralValid(ui32Peripheral));

    // Enable this peripheral in sleep mode.
    HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
        PRCM_PERIPH_MASKBIT(ui32Peripheral);
}

void PRCMPowerDomainOff

(

uint32_t

ui32Domains

)

Turn off a specific power domain.

Use this function to power down domains inside the MCU voltage domain.

Note

For specifics regarding on/off configuration please see PRCMPowerDomainOn().

Parameters

ui32Domains

determines which domain to request a power down for. The domains that can be turned on/off are: PRCM_DOMAIN_RFCORE : RF Core PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM PRCM_DOMAIN_SYSBUS PRCM_DOMAIN_CPU

Returns

None

Referenced by SysCtrlIdle(), and SysCtrlStandby().

{
    // Check the arguments.
    ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
           (ui32Domains & PRCM_DOMAIN_SERIAL) ||
           (ui32Domains & PRCM_DOMAIN_PERIPH) ||
           (ui32Domains & PRCM_DOMAIN_CPU) ||
           (ui32Domains & PRCM_DOMAIN_VIMS));

    // Assert the request to power off the right domains.
    if(ui32Domains & PRCM_DOMAIN_RFCORE)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC   ) = 0;
    }
    if(ui32Domains & PRCM_DOMAIN_SERIAL)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0;
    }
    if(ui32Domains & PRCM_DOMAIN_PERIPH)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0;
    }
    if(ui32Domains & PRCM_DOMAIN_VIMS)
    {
        // Write bits ui32Domains[17:16] to the VIMS_MODE alias register.
        // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10.
        ASSERT(!(ui32Domains & 0x00010000));
        HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS  ) = ( ui32Domains >> 16 ) & 3;
    }
    if(ui32Domains & PRCM_DOMAIN_CPU)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU   ) = 0;
    }
}

void PRCMPowerDomainOn

(

uint32_t

ui32Domains

)

Turn power on in power domains in the MCU domain.

Use this function to turn on power domains inside the MCU voltage domain.

Power on and power off request has different implications for the different power domains.

• RF Core power domain:
  • Power On : Domain is on or in the process of turning on.
  • Power Off : Domain is powered down when System CPU is in deep sleep. The third option for the RF Core is to power down when the it is idle. This can be set using PRCMRfPowerDownWhenIdle()
• SERIAL power domain:
  • Power on : Domain is powered on.
  • Power off : Domain is powered off.
• PERIPHERIAL power domain:
  • Power on : Domain is powered on.
  • Power off : Domain is powered off.
• VIMS power domain:
  • Power On : Domain is powered if Bus domain is powered.
  • Power Off : Domain is only powered when CPU domain is on.
• BUS power domain:
  • Power On : Domain is on.
  • Power Off : Domain is on if requested by RF Core or if CPU domain is on.
• CPU power domain:
  • Power On : Domain is on.
  • Power Off : Domain is powering down if System CPU is idle. This will also initiate a power down of the SRAM and BUS power domains, unless RF Core is requesting them to be on.

Note

After a call to this function the status of the power domain should be checked using either PRCMPowerDomainStatus(). Any write operation to a power domain which is still not operational can result in unexpected behavior.

Parameters

ui32Domains

determines which power domains to turn on. The domains that can be turned on/off are: PRCM_DOMAIN_RFCORE : RF Core PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM PRCM_DOMAIN_SYSBUS PRCM_DOMAIN_CPU

Returns

None

{
    // Check the arguments.
    ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
           (ui32Domains & PRCM_DOMAIN_SERIAL) ||
           (ui32Domains & PRCM_DOMAIN_PERIPH) ||
           (ui32Domains & PRCM_DOMAIN_CPU) ||
           (ui32Domains & PRCM_DOMAIN_VIMS));

    // Assert the request to power on the right domains.
    if(ui32Domains & PRCM_DOMAIN_RFCORE)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC   ) = 1;
    }
    if(ui32Domains & PRCM_DOMAIN_SERIAL)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1;
    }
    if(ui32Domains & PRCM_DOMAIN_PERIPH)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1;
    }
    if(ui32Domains & PRCM_DOMAIN_VIMS)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS  ) = 1;
    }
    if(ui32Domains & PRCM_DOMAIN_CPU)
    {
        HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU   ) = 1;
    }
}

uint32_t PRCMPowerDomainStatus

(

uint32_t

ui32Domains

)

Get the status for a specific power domain.

Use this function to retrieve the current power status of one or more power domains.

Parameters

ui32Domains

determines which domain to get the power status for. The parameter must be an OR'ed combination of one or several of: PRCM_DOMAIN_RFCORE : RF Core. PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1

Returns

Returns status of the requested domains:

• PRCM_DOMAIN_POWER_ON : The specified domains are all powered up. This status is unconditional and the powered up status is guaranteed.
• PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down.

Referenced by SysCtrlStandby().

{
    bool bStatus;
    uint32_t ui32StatusRegister0;
    uint32_t ui32StatusRegister1;

    // Check the arguments.
    ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE |
                           PRCM_DOMAIN_SERIAL |
                           PRCM_DOMAIN_PERIPH)));

    bStatus = true;
    ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0);
    ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1);

    // Return the correct power status.
    if(ui32Domains & PRCM_DOMAIN_RFCORE)
    {
       bStatus = bStatus &&
                 ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) ||
                  (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON));
    }
    if(ui32Domains & PRCM_DOMAIN_SERIAL)
    {
        bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON);
    }
    if(ui32Domains & PRCM_DOMAIN_PERIPH)
    {
        bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON);
    }

    // Return the status.
    return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF);
}

static void PRCMRfPowerDownWhenIdle ( void  )

inlinestatic

Configure RF core to power down when idle.

Use this function to configure the RF core to power down when Idle. This is handled automatically in hardware if the RF Core reports that it is idle.

Returns

None

{
    // Configure the RF power domain.
    HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0;
}

static bool PRCMRfReady ( void  )

inlinestatic

Return the access status of the RF Core.

Use this function to check if the RF Core is on and ready to be accessed. Accessing register or memories that are not powered and clocked will cause a bus fault.

Returns

Returns access status of the RF Core.

• true : RF Core can be accessed.
• false : RF Core domain is not ready for access.

{
    // Return the ready status of the RF Core.
    return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) &
             PRCM_PDSTAT1RFC_ON) ? true : false);
}

static void PRCMSleep ( void  )

inlinestatic

Put the processor into sleep mode.

This function places the processor into sleep mode; it does not return until the processor returns to run mode. The peripherals that are enabled via PRCMPeripheralSleepEnable() continue to operate and can wake up the processor.

Returns

None

See also

PRCMPeripheralSleepEnable()

{
    // Wait for an interrupt.
    CPUwfi();
}

Here is the call graph for this function:

Macro Definition Documentation

#define I2S_SAMPLE_RATE_16K   0x00000001

Referenced by PRCMAudioClockConfigSet().

#define I2S_SAMPLE_RATE_24K   0x00000002

Referenced by PRCMAudioClockConfigSet().

#define I2S_SAMPLE_RATE_32K   0x00000004

Referenced by PRCMAudioClockConfigSet().

#define I2S_SAMPLE_RATE_48K   0x00000008

Referenced by PRCMAudioClockConfigSet().

#define PRCM_CLOCK_DIV_1   PRCM_GPTCLKDIV_RATIO_DIV1

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_CLOCK_DIV_128   PRCM_GPTCLKDIV_RATIO_DIV128

#define PRCM_CLOCK_DIV_16   PRCM_GPTCLKDIV_RATIO_DIV16

#define PRCM_CLOCK_DIV_2   PRCM_GPTCLKDIV_RATIO_DIV2

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_CLOCK_DIV_256   PRCM_GPTCLKDIV_RATIO_DIV256

#define PRCM_CLOCK_DIV_32   PRCM_GPTCLKDIV_RATIO_DIV32

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_CLOCK_DIV_4   PRCM_GPTCLKDIV_RATIO_DIV4

#define PRCM_CLOCK_DIV_64   PRCM_GPTCLKDIV_RATIO_DIV64

#define PRCM_CLOCK_DIV_8   PRCM_GPTCLKDIV_RATIO_DIV8

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_DEEP_SLEEP_MODE   0x00000004

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_DOMAIN_CLKCTRL   0x00000080

#define PRCM_DOMAIN_CPU   0x00000020

Referenced by PRCMPowerDomainOff(), PRCMPowerDomainOn(), SysCtrlIdle(), and SysCtrlStandby().

#define PRCM_DOMAIN_MCU   0x00000100

#define PRCM_DOMAIN_PERIPH   0x00000004

Referenced by PRCMPowerDomainOff(), PRCMPowerDomainOn(), PRCMPowerDomainStatus(), and SysCtrlStandby().

#define PRCM_DOMAIN_POWER_DOWN_READY   0x00000000

#define PRCM_DOMAIN_POWER_OFF   0x00000002

Referenced by PRCMPowerDomainStatus(), and SysCtrlStandby().

#define PRCM_DOMAIN_POWER_ON   0x00000001

Referenced by PRCMPowerDomainStatus().

#define PRCM_DOMAIN_RFCORE   0x00000001

Referenced by PRCMDomainDisable(), PRCMDomainEnable(), PRCMPowerDomainOff(), PRCMPowerDomainOn(), PRCMPowerDomainStatus(), and SysCtrlStandby().

#define PRCM_DOMAIN_SERIAL   0x00000002

Referenced by PRCMPowerDomainOff(), PRCMPowerDomainOn(), PRCMPowerDomainStatus(), and SysCtrlStandby().

#define PRCM_DOMAIN_SYSBUS   0x00000008

#define PRCM_DOMAIN_TIMER   0x00000040

#define PRCM_DOMAIN_VIMS   0x00000010

Referenced by PRCMDomainDisable(), PRCMDomainEnable(), PRCMPowerDomainOff(), and PRCMPowerDomainOn().

#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP   0x00020010

#define PRCM_PERIPH_CRYPTO   ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S ))

Referenced by SysCtrlStandby().

#define PRCM_PERIPH_GPIO   ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S ))

#define PRCM_PERIPH_I2C0   ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S ))

#define PRCM_PERIPH_I2S   ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S ))

Referenced by SysCtrlStandby().

#define PRCM_PERIPH_PKA   ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S ))

#define PRCM_PERIPH_SSI0   ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S ))

#define PRCM_PERIPH_SSI1   ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 ))

#define PRCM_PERIPH_TIMER0   ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S ))

#define PRCM_PERIPH_TIMER1   ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 ))

#define PRCM_PERIPH_TIMER2   ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 ))

#define PRCM_PERIPH_TIMER3   ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 ))

#define PRCM_PERIPH_TRNG   ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S ))

#define PRCM_PERIPH_UART0   ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S ))

#define PRCM_PERIPH_UART1   ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 ))

#define PRCM_PERIPH_UDMA   ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S ))

Referenced by SysCtrlStandby().

#define PRCM_RUN_MODE   0x00000001

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_SLEEP_MODE   0x00000002

Referenced by PRCMInfClockConfigureGet(), and PRCMInfClockConfigureSet().

#define PRCM_WCLK_DUAL_PHASE   0x00000002

#define PRCM_WCLK_NEG_EDGE   0x00000008

#define PRCM_WCLK_POS_EDGE   0x00000000

#define PRCM_WCLK_SINGLE_PHASE   0x00000000

Referenced by PRCMAudioClockConfigSet(), and PRCMAudioClockConfigSetOverride().

#define PRCM_WCLK_USER_DEF   0x00000004