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xWRL6432 MMWAVE-L-SDK
05.04.00.01
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33 #ifndef SOC_RCM_XWRL64XX_H
34 #define SOC_RCM_XWRL64XX_H
54 #define SOC_RCM_FREQ_HZ2MHZ(hz) ((hz)/(1000000U))
55 #define SOC_RCM_FREQ_MHZ2HZ(mhz) ((mhz)*(1000000U))
57 #define SOC_RCM_MEMINIT_APPSS_RAM1A_INIT (1U << 0U)
58 #define SOC_RCM_MEMINIT_APPSS_RAM2A_INIT (1U << 1U)
59 #define SOC_RCM_MEMINIT_APPSS_RAM3A_INIT (1U << 2U)
60 #define SOC_RCM_MEMINIT_APPSS_ALL_INIT (SOC_RCM_MEMINIT_APPSS_RAM1A_INIT | \
61 SOC_RCM_MEMINIT_APPSS_RAM2A_INIT | \
62 SOC_RCM_MEMINIT_APPSS_RAM3A_INIT)
64 #define SOC_RCM_MEMINIT_APPSS_SHRAM0_INIT (0x1U)
65 #define SOC_RCM_MEMINIT_APPSS_SHRAM1_INIT (0x1U << 1U)
66 #define SOC_RCM_MEMINIT_HWA_SHRAM_INIT (0x1U << 2U)
67 #define SOC_RCM_MEMINIT_FECSS_SHRAM_INIT (0x1U << 3U)
68 #define SOC_RCM_MEMINIT_TPCCA_INIT (0x1U << 8U)
69 #define SOC_RCM_MEMINIT_TPCCB_INIT (0x1U << 9U)
81 #define SOC_RCM_EFUSEROM_VER_2 ((uint8_t)(0x02U))
86 typedef enum SOC_RcmResetCause_e
122 typedef enum SOC_RcmPeripheralId_e
198 typedef enum SOC_RcmPeripheralClockSource_e
242 typedef enum SOC_RcmM4ClockSource_e
254 typedef enum SOC_RcmQspiClockFreqId_e {
277 typedef enum SOC_RcmPeripheralClockGate_e {
@ SOC_RcmM4ClockSource_SLOW_CLK
Definition: soc_rcm.h:245
@ SOC_RcmQspiClockFreqId_CLK_80MHZ
Value specifying QSPI clock of 80 Mhz.
Definition: soc_rcm.h:266
SOC_RcmPeripheralClockGate
Peripheral Clock Gate Status.
Definition: soc_rcm.h:277
@ SOC_RcmPeripheralClockSource_OSC_CLK
Value specifying Crystal Clock (40MHz)
Definition: soc_rcm.h:203
@ SOC_RcmResetCause_POWER_CAUSE_CLEAR
Value specifying Reset Cause Clear.
Definition: soc_rcm.h:91
uint8_t SOC_rcmReadAPLLCalibTrimValid(void)
Reads APLL_CALIB_TRIM_VALID field from TOP Efuse memory.
void SOC_rcmEnableADPLLClock()
Enable ADPLL.
@ SOC_rcmM4ClockSrc_SLOW_CLK
Definition: soc_rcm.h:76
uint8_t SOC_rcmReadSynthTrimValid(void)
Reads SYNTH_TRIM_VALID field from TOP Efuse memory.
@ SOC_rcmM4ClockSrc_OSC_CLK
Definition: soc_rcm.h:75
void SOC_rcmStartMemInitTpcc(uint16_t flag)
Start memory initialization for TPCCA and TPCCB.
SOC_RcmPeripheralClockSource
Peripheral Clock Sources.
Definition: soc_rcm.h:199
@ SOC_RcmPeripheralClockSource_RC_CLK_10M
Value specifying RC_CLK_10M Clock (10Mhz)
Definition: soc_rcm.h:227
@ SOC_RcmPeripheralClockSource_XREF_IN_CLK
Value specifying XREF_IN Clock (40MHz)
Definition: soc_rcm.h:219
@ SOC_rcmM4ClockSrc_FAST_CLK
Definition: soc_rcm.h:78
@ SOC_RcmPeripheralId_APPSS_LIN
Value specifying LIN.
Definition: soc_rcm.h:131
@ SOC_RcmPeripheralId_APPSS_PWM
Value specifying APPSS PWM.
Definition: soc_rcm.h:179
uint8_t SOC_getEfusePgVersion(void)
Reads PG_VER field from TOP Efuse memory.
@ SOC_RcmPeripheralClockSource_FAST_CLK
Value specifying Fast Clock (160Mhz)
Definition: soc_rcm.h:215
@ SOC_RcmPeripheralId_APPSS_QSPI
Value specifying QSPI (Quad SPI)
Definition: soc_rcm.h:135
@ SOC_rcmM4ClockSrc_MDLL_CLK
Definition: soc_rcm.h:77
SOC_RcmQspiClockFreqId
QSPI frequency values.
Definition: soc_rcm.h:254
@ SOC_RcmPeripheralId_APPSS_RTI
Value specifying APPSS RTIA (Timer)
Definition: soc_rcm.h:139
SOC_RcmResetCause SOC_rcmGetResetCause(void)
Get SOC reset cause.
@ SOC_RcmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:95
@ SOC_RcmPeripheralClockSource_MDLL_CLK
Value specifying MDLL Clock (160Mhz)
Definition: soc_rcm.h:211
SOC_RcmPeripheralId
Peripheral IDs.
Definition: soc_rcm.h:123
uint32_t SOC_rcmGetM4Clock(void)
Get M4 frequency.
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
Set peripheral frequency.
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockGate enable)
Enable/Disable peripheral Clock gating.
@ SOC_RcmResetCause_CORE_RESET
Value specifying M4 Core Reset.
Definition: soc_rcm.h:111
void SOC_rcmWaitMemInitTpcc(uint16_t flag)
Wait memory initialization to complete TPCCA and TPCCB.
@ SOC_RcmResetCause_CPU_ONLY_RESET
Value specifying M4 CPU Reset.
Definition: soc_rcm.h:107
@ SOC_RcmPeripheralId_HWASS
Value specifying HWASS.
Definition: soc_rcm.h:187
@ SOC_RcmPeripheralId_APPSS_WDT
Value specifying APPSS WatchDog.
Definition: soc_rcm.h:143
@ SOC_RcmPeripheralId_MAX_VALUE
max value
Definition: soc_rcm.h:191
SOC_RcmResetCause
Reset Causes.
Definition: soc_rcm.h:87
@ SOC_RcmPeripheralId_APPSS_I2C
Value specifying APPSS I2C.
Definition: soc_rcm.h:155
@ SOC_RcmM4ClockSource_MDLL_CLK
Definition: soc_rcm.h:246
@ SOC_RcmPeripheralClockSource_MAX_VALUE
max value
Definition: soc_rcm.h:235
@ SOC_RcmPeripheralClockGateEnable
Peripheral Clock Ungate.
Definition: soc_rcm.h:281
int32_t SOC_rcmSetM4Clock(uint32_t m4FreqHz)
Set M4 frequency.
@ SOC_RcmPeripheralId_APPSS_ESM
Value specifying APPSS ESM.
Definition: soc_rcm.h:167
@ SOC_RcmPeripheralId_APPSS_CRC
Value specifying APPSS CRC.
Definition: soc_rcm.h:175
@ SOC_RcmPeripheralId_APPSS_UART0
Value specifying APPSS SCI-A (UART)
Definition: soc_rcm.h:159
SOC_rcmM4ClockSrc
Definition: soc_rcm.h:75
int32_t SOC_rcmSetM4ClockSrc(SOC_rcmM4ClockSrc m4Src)
Set M4 Clock Source.
void SOC_rcmWaitMemInitSharedRam(uint16_t flag)
Wait memory initialization to complete APSS Shared Memory RAM0, RAM1 and HWA Shared RAM.
@ SOC_RcmPeripheralClockSource_RCCLK32K
Value specifying RCCLK32K Clock (32KHz)
Definition: soc_rcm.h:231
@ SOC_RcmPeripheralClockGateDisable
Peripheral Clock Gate.
Definition: soc_rcm.h:285
@ SOC_RcmPeripheralClockSource_SLOW_CLK
Value specifying Slow Clock (33Khz)
Definition: soc_rcm.h:207
@ SOC_RcmM4ClockSource_MAX_VALUE
Definition: soc_rcm.h:248
@ SOC_RcmM4ClockSource_FAST_CLK
Definition: soc_rcm.h:247
@ SOC_RcmQspiClockFreqId_CLK_40MHZ
Value specifying QSPI clock of 40 Mhz.
Definition: soc_rcm.h:258
@ SOC_RcmPeripheralId_APPSS_MCSPIB
Value specifying APPSS SPI-1.
Definition: soc_rcm.h:151
uint8_t SOC_isDeviceAOP(void)
Reads ANTENNA TYPE field from TOP Efuse memory.
@ SOC_RcmM4ClockSource_OSC_CLK
Definition: soc_rcm.h:244
@ SOC_RcmPeripheralId_APPSS_UART1
Value specifying APPSS SCI-B (UART)
Definition: soc_rcm.h:163
@ SOC_RcmResetCause_STC_RESET
Value specifying STC Reset.
Definition: soc_rcm.h:103
@ SOC_RcmPeripheralId_APPSS_MCAN
Value specifying CAN.
Definition: soc_rcm.h:127
@ SOC_RcmResetCause_WARM_RESET
Value specifying Warm Reset or Subsystem Reset.
Definition: soc_rcm.h:99
@ SOC_RcmQspiClockFreqId_CLK_60MHZ
Value specifying QSPI clock of 60 Mhz.
Definition: soc_rcm.h:262
SOC_RcmM4ClockSource
M4 Clock Sources.
Definition: soc_rcm.h:243
uint32_t SOC_rcmGetPeripheralClock(SOC_RcmPeripheralId periphId)
Get peripheral frequency.
@ SOC_RcmQspiClockFreqId_MAX_VALUE
max value
Definition: soc_rcm.h:270
@ SOC_RcmPeripheralId_APPSS_EDMA
Value specifying APPSS EDMA.
Definition: soc_rcm.h:171
@ SOC_RcmResetCause_MAX_VALUE
max value
Definition: soc_rcm.h:115
@ SOC_RcmPeripheralId_APPSS_MCSPIA
Value specifying APPSS SPI-0.
Definition: soc_rcm.h:147
uint8_t SOC_getEfuseRomVersion(void)
Reads EFUSEROM_VER from TOP Efuse memory.
@ SOC_RcmPeripheralId_APPSS_GIO
Value specifying APPSS PWM.
Definition: soc_rcm.h:183
@ SOC_RcmPeripheralClockSource_OSC_CLKX2
Value specifying OSC_CLKx2 Clock (80Mhz)
Definition: soc_rcm.h:223
void SOC_rcmStartInitSharedRam(uint16_t flag)
Start memory initialization for APPSS Shared Memory RAM0, RAM1 and HWASS Shared RAM.