CacheP.h

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/*
 *  Copyright (C) 2018-2021 Texas Instruments Incorporated
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#ifndef CACHEP_H
#define CACHEP_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
 
#define CacheP_CACHELINE_ALIGNMENT   (128U)
 
typedef enum CacheP_Type_ {
    CacheP_TYPE_L1P  = (0x0001u), 
    CacheP_TYPE_L1D  = (0x0002u), 
    CacheP_TYPE_L2P  = (0x0004u), 
    CacheP_TYPE_L2D  = (0x0008u), 
    CacheP_TYPE_L1   = (CacheP_TYPE_L1P|CacheP_TYPE_L1D), 
    CacheP_TYPE_L2   = (CacheP_TYPE_L2P|CacheP_TYPE_L2D), 
    CacheP_TYPE_ALLP = (CacheP_TYPE_L1P|CacheP_TYPE_L2P), 
    CacheP_TYPE_ALLD = (CacheP_TYPE_L1D|CacheP_TYPE_L2D), 
    CacheP_TYPE_ALL  = (CacheP_TYPE_L1|CacheP_TYPE_L2)    
} CacheP_Type;
 
typedef struct CacheP_Config_ {
 
    uint32_t enable;    
    uint32_t enableForceWrThru; 
} CacheP_Config;
 
extern CacheP_Config    gCacheConfig;
 
void CacheP_enable(uint32_t type);
 
void CacheP_disable(uint32_t type);
 
uint32_t CacheP_getEnabled();
 
void CacheP_wbAll(uint32_t type);
 
void CacheP_wbInvAll(uint32_t type);
 
void CacheP_wb(void *addr, uint32_t size, uint32_t type);
 
void CacheP_inv(void *addr, uint32_t size, uint32_t type);
 
void CacheP_wbInv(void *addr, uint32_t size, uint32_t type);
 
void CacheP_init();
 
#ifdef __cplusplus
}
#endif
 
#endif /* CACHEP_H */