5.6.7.2. AM64x Peripheral Interrupt Destination Descriptions¶
5.6.7.2.1. Introduction¶
This chapter provides information on processor interrupt destination IDs that are permitted in the am64x SoC. The interrupt destination IDs represent inputs to SoC processor interrupt controllers or the processors themselves. The System Firmware interrupt management TISCI message APIs take interrupt destination IDs as input to set and release interrupt routes between source peripherals and destination processors.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
5.6.7.2.2. Interrupt Destination IDs¶
Destination Device Name | Destination Device ID | Interrupt Destination Description | Interrupt Destination Input Index |
---|---|---|---|
AM64X_DEV_MCU_M4FSS0_CORE0 | 9 | AM64X_DEV_MCU_M4FSS0_CORE0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 0 to 3 |
AM64X_DEV_MCU_M4FSS0_CORE0 | 9 | AM64X_DEV_MCU_M4FSS0_CORE0 inputs from DMASS0_INTAGGR_0 | 32 to 47 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 0 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 1 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 2 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 3 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 4 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 5 |
AM64X_DEV_CPSW0 | 13 | AM64X_DEV_CPSW0 inputs from TIMESYNC_EVENT_INTROUTER0 | 6 |
AM64X_DEV_DMASS0_INTAGGR_0 | 28 | AM64X_DEV_DMASS0_INTAGGR_0 inputs from CMP_EVENT_INTROUTER0 | 0 to 7 |
AM64X_DEV_DMASS0_INTAGGR_0 | 28 | AM64X_DEV_DMASS0_INTAGGR_0 inputs from TIMESYNC_EVENT_INTROUTER0 | 8 to 15 |
AM64X_DEV_DMASS0_INTAGGR_0 | 28 | AM64X_DEV_DMASS0_INTAGGR_0 inputs from MAIN_GPIOMUX_INTROUTER0 | 16 to 25 |
AM64X_DEV_MCU_ESM0 | 64 | AM64X_DEV_MCU_ESM0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 88 to 91 |
AM64X_DEV_MCU_ESM0 | 64 | AM64X_DEV_MCU_ESM0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 92 to 95 |
AM64X_DEV_MCU_ESM0 | 64 | AM64X_DEV_MCU_ESM0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 96 to 99 |
AM64X_DEV_GICSS0 | 76 | AM64X_DEV_GICSS0 inputs from MAIN_GPIOMUX_INTROUTER0 | 32 to 47 |
AM64X_DEV_GICSS0 | 76 | AM64X_DEV_GICSS0 inputs from CMP_EVENT_INTROUTER0 | 48 to 63 |
AM64X_DEV_GICSS0 (Reserved by System Firmware) | 76 | AM64X_DEV_GICSS0 inputs from DMASS0_INTAGGR_0 | 64 to 67 |
AM64X_DEV_GICSS0 | 76 | AM64X_DEV_GICSS0 inputs from DMASS0_INTAGGR_0 | 68 to 103 |
AM64X_DEV_GICSS0 | 76 | AM64X_DEV_GICSS0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 104 to 107 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from TIMESYNC_EVENT_INTROUTER0 | 0 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from TIMESYNC_EVENT_INTROUTER0 | 1 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from TIMESYNC_EVENT_INTROUTER0 | 2 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from TIMESYNC_EVENT_INTROUTER0 | 3 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from MAIN_GPIOMUX_INTROUTER0 | 4 to 9 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from MAIN_GPIOMUX_INTROUTER0 | 10 to 15 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from DMASS0_INTAGGR_0 | 16 to 23 |
AM64X_DEV_PRU_ICSSG0 | 81 | AM64X_DEV_PRU_ICSSG0 inputs from MAIN_GPIOMUX_INTROUTER0 | 46 to 53 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from TIMESYNC_EVENT_INTROUTER0 | 0 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from TIMESYNC_EVENT_INTROUTER0 | 1 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from TIMESYNC_EVENT_INTROUTER0 | 2 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from TIMESYNC_EVENT_INTROUTER0 | 3 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from MAIN_GPIOMUX_INTROUTER0 | 4 to 9 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from MAIN_GPIOMUX_INTROUTER0 | 10 to 15 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from DMASS0_INTAGGR_0 | 16 to 23 |
AM64X_DEV_PRU_ICSSG1 | 82 | AM64X_DEV_PRU_ICSSG1 inputs from MAIN_GPIOMUX_INTROUTER0 | 46 to 53 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 0 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 1 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 2 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 3 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 4 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 5 |
AM64X_DEV_CPTS0 | 84 | AM64X_DEV_CPTS0 inputs from TIMESYNC_EVENT_INTROUTER0 | 6 |
AM64X_DEV_R5FSS0_CORE0 | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from DMASS0_INTAGGR_0 | 8 to 15 |
AM64X_DEV_R5FSS0_CORE0 | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from MAIN_GPIOMUX_INTROUTER0 | 32 to 47 |
AM64X_DEV_R5FSS0_CORE0 | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from CMP_EVENT_INTROUTER0 | 48 to 55 |
AM64X_DEV_R5FSS0_CORE0 (Reserved by System Firmware) | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from DMASS0_INTAGGR_0 | 64 to 65 |
AM64X_DEV_R5FSS0_CORE0 | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from DMASS0_INTAGGR_0 | 66 to 95 |
AM64X_DEV_R5FSS0_CORE0 | 121 | AM64X_DEV_R5FSS0_CORE0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 104 to 107 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from DMASS0_INTAGGR_0 | 8 to 15 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from MAIN_GPIOMUX_INTROUTER0 | 32 to 47 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from CMP_EVENT_INTROUTER0 | 48 to 55 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from DMASS0_INTAGGR_0 | 64 to 65 |
AM64X_DEV_R5FSS0_CORE1 (Reserved by System Firmware) | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from DMASS0_INTAGGR_0 | 66 to 67 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from DMASS0_INTAGGR_0 | 68 to 95 |
AM64X_DEV_R5FSS0_CORE1 | 122 | AM64X_DEV_R5FSS0_CORE1 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 104 to 107 |
AM64X_DEV_R5FSS1_CORE0 | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from DMASS0_INTAGGR_0 | 8 to 15 |
AM64X_DEV_R5FSS1_CORE0 | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from MAIN_GPIOMUX_INTROUTER0 | 32 to 47 |
AM64X_DEV_R5FSS1_CORE0 | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from CMP_EVENT_INTROUTER0 | 48 to 55 |
AM64X_DEV_R5FSS1_CORE0 (Reserved by System Firmware) | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from DMASS0_INTAGGR_0 | 64 to 65 |
AM64X_DEV_R5FSS1_CORE0 | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from DMASS0_INTAGGR_0 | 66 to 95 |
AM64X_DEV_R5FSS1_CORE0 | 123 | AM64X_DEV_R5FSS1_CORE0 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 104 to 107 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from DMASS0_INTAGGR_0 | 8 to 15 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from MAIN_GPIOMUX_INTROUTER0 | 32 to 47 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from CMP_EVENT_INTROUTER0 | 48 to 55 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from DMASS0_INTAGGR_0 | 64 to 65 |
AM64X_DEV_R5FSS1_CORE1 (Reserved by System Firmware) | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from DMASS0_INTAGGR_0 | 66 to 67 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from DMASS0_INTAGGR_0 | 68 to 95 |
AM64X_DEV_R5FSS1_CORE1 | 124 | AM64X_DEV_R5FSS1_CORE1 inputs from MCU_MCU_GPIOMUX_INTROUTER0 | 104 to 107 |