6.3. Hardware Setup with CCS¶

6.3.1. AM572x GP EVM Hardware Setup¶

Description

The AM572x Evaluation Module provides an affordable platform to quickly start evaluation of Sitara™ ARM® Cortex®-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. It is a development platform based on the dual ARM Cortex-A15, dual C66x DSP processor that is integrated with tons of connectivity such as PCIe, SATA, HDMI, USB 3.0/2.0, Dual Gigabit Ethernet, and more.

The AM572x Evaluation Module also integrates video and 3D/2D graphics acceleration, as well as a qual-core Programmable Real-time Unit (PRU) and dual ARM Cortex-M4 cores.

Contents of the kit

Module:

• Processor Module
• LCD Module
• Camera Module

Other components:

• µSD card with Linux SDK
• USB-to-serial debug cable
• HDMI cable for optional external display
• LCD brackets

Printed documentation:

• Quick start guide

EVM Layout and Key Components

JTAG debug probes (aka Emulators) supported

List of standalone JTAG debug probes supported:

• XDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.
• XDS200-class JTAG debug probes (recommended)
• XDS560v2-class JTAG debug probes (high performance)

Host Drivers

Download and install Virtual COM Port Drivers for TTL-232R-3V3 USB to UART cable from the FTDI website:

• VCP Drivers
• TTL-232R-3V3 product

Minimal EVM setup

Setting boot switches

Other Boot Pin configurations: GP EVM Boot Options

Connecting Emulator

Note: This EVM setup is only required for developers who need to connect to cores using Code Composer studio to load application.

The JTAG emulation pins for the EVM are on the back of the processor module. User need to carefully unmount the processor module from the LCD panel in order to get access to the JTAG pins.

Refer to the image below for how to safely separate the processor module from the LCD panel.

Powering up the EVM

Power Supply specifications

Please note that a power supply is NOT included with the AM572x Evaluation Module and needs to be purchased separately. A power supply with the following specs is needed:

• 12V DC output
• 5A output
• Positive inner and negative outer terminals
• Female barrel with 2.5mm inner diameter and 5.5mm outer diameter
• Isolated power supply

PMIC auto-off after seven seconds

The Power Management Integrated Circuit (PMIC) on the TMDSEVM572X turns off the board in seven seconds after power on to work around a hardware errata. After seven seconds, the PMIC powers off unless software writes to a PMIC register to keep it on.

In emulation setup, the GEL file will keep the PMIC on after you connect to the A15 core on the SoC. While booting from ROM bootloader user application software, would need to keep the PMIC ON while initializing the board.

In Linux boot, the uboot code keeps the PMIC On and in the TI RTOS boot scenario, the SBL component provides the same functionality

NOTE

• To allow quicker execution of the GEL before the PMIC shuts off, you can increase the JTAG TCLK Frequency in Advance settings of your target configuration to 15Mhz or to the maximum (20Mhz).
• If the above CCS connect sequence does not work in the first attempt, it means that the PMIC switched off before the GEL could initialize I2C and modify the PMIC settings. In that case, the connection has failed, hit connect in CCS debug view without removing the power cable and then immediately hit the power switch besides the power plug.

Connect Power to the EVM

CCS Setup

There are two scenarios while connecting to the EVM :

• Connect to EVM without a SD card boot image to boot the EVM
• Connect to EVM after booting an image from the SD card.

Connect without a SD card boot image

Configuring target configuration files

Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as GPEVM_AM572x_SiRevA.

Note: For older revisions of CCSv6, If you don`t find the GPEVM_AM572x_SiRevA target make sure you have installed the CCSv6 package with support for Sitara Processors and done the software update correctly from the Help Menu to get the latest Sitara CSP package.

In advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:

• IcePick_D: AM572x_ICEPickD_Utility.gel
• CS_DAP_DebugSS: AM572x_dap_startup.gel
• CS_DAP_PC: AM572x_CS_DAP_PC_Utility.gel
• A15_0: AM572x_cortexa15_cpu0_startup.gel
• A15_1: AM572x_cortexa15_cpu1_startup.gel
• C66x_0: AM572x_dsp_startup.gel
• C66x_1: AM572x_dsp_startup.gel
• M4_IPU_1_C0: AM572x_cortexM4_startup.gel
• M4_IPU_1_C1: AM572x_cortexM4_startup.gel
• M4_IPU_2_C0: AM572x_cortexM4_startup.gel
• M4_IPU_2_C1: AM572x_cortexM4_startup.gel
• IVAHD: AM572x_ivahd_startup.gel

Connecting to target

Step1 : Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:

Install Code composer Studio v6 for AM572x

Step2: AM572x EVM doesn`t have any boot switches to configure for emulation mode. so configure the boot switches to SD Boot Mode. Dont Populate the uSD card when the intent is to connect and load code over emulator and not to boot the device using uSD card.

Step3: Connect an XDS200 Emulator to emulation pins at the back of the GP EVM as shown in section.Connecting_Emulator

Step4: Launch CCS and create new target configuration as discussed in the previous section.

IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output:    Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output:    Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output:    PER DPLL already locked, now unlocking
CortexA15_0: GEL Output:    PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    CORE DPLL OPP  already locked, now unlocking....
CortexA15_0: GEL Output:    CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output:    ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output:    DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output:    DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Two EMIFs in interleaved mode - (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: >> START ==> Enable L3 Clk
CortexA15_0: GEL Output: >> Change Suspend source for GPTimer5 to DSP1
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

Multi-core Initialization

After connecting to the boot master core – typically the ARM core – you may need to connect to a slave core in order to run code. Depending on your SOC, the slave core can be

• DSP C66x
• ARM M4
• PRUSS
• IVAHD

Typically the slave cores will wait in reset state until the master core wakes up the slave core to run code. To connect to the slave core on AM57x, go to Scripts menu in CCS Debug View and under AM572x MULTICORE Initialization enable the corresponding sub system clock. For example, enable DSP11SSClkEnable_API for the first DSP core. After running the clock enable option, you can connect to the core.

If you wish to run TI RTOS code on DSP, please also run the Timer Suspend Control Options.

Connect after booting from SD card

When you boot an image from the SD card, the secondary boot loader will configure the device clocks, DDR and wake up the slave cores on the AM572x processor on GP EVM hence you don`t need the GEL initialization scripts to redo the clock and DDR settings.

Note: If you are running the Image processing demo or have created an SD card with the SBL (mlo) for booting the board then please follow the following procedure

Configuring target configuration files

Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Spectrum digital XDS200 emulator and target as AM5728_RevA. This target setting will not populate the GEL files when you connect to the target

Note: If you don`t find the AM572x_RevA target make sure you have installed the CCSv6.1.1 package and done the software update correctly.

GEL file options

Changing SoC Operating point

The GEL file for setting the clocks on the SoC provides 3 Operating points OPP_NOM, OPP_OD and OPP_HIGH.

OPP_NOM PLL Settings:

• ARM = 1000 MHz
• DSP = 600 Mhz
• IVA = 532 Mhz

OPP_OD PLL Settings:

• ARM = 1176 MHz
• DSP = 600 Mhz
• IVA = 430 Mhz
• GPU =500 Mhz

OPP_HIGH PLL Settings:

• ARM = 1500 MHz
• DSP = 700 Mhz
• GPU = 425 Mhz
• IVA = 388.3 Mhz

Timer Suspend Control Options for DSP

On AM57xx devices, all the timers on the chip have their suspend control signal routed to the A15 core. Which means that if any of the slave cores are using these timers, the timers will continue to run even when the slave core has been paused. The timer will only pause when the A15 core is halted.

This is confusing while debugging code on slave cores if you are relying on timer for logging, inserting delays or if the timer keeps firing interrupts even when the core is halted. One such scenario occurs with GPtimer5 when DSP developers are using SYS/BIOS. The OS uses GPtimer5 on the DSP and forces a frequency check to confirm the timer configuration, however the OS can’t gain access to the timer due to the hook up of the suspend control signals.

Due to this issue the SYS/BIOS developers will need to configure an additional CCS configuration check to connect the GPTimer suspend control signal to the DSP as shown in the image below:

Other How-To Options

Connecting the UART

Connecting FTDI cable to the 6 pin UART header for serial debug

Note: Pin 1 corresponds to ground.

Connect the USB end to the host. If you connect to the EVM UART, use the following host configuration setup in the serial terminal software (Minicom, Teraterm, etc) Baud Rate: 115200 Data Bits: 8 Parity: None Flow Control: Off

Connect Ethernet cable to enable Network Connectivity

For ethernet connectivity connect the ethernet cable to the top serial port which is port 0 on the GP EVM.

You can connect the other end of the cable directly to the host or through a network switch based on the configuration required for your test setup.

6.3.2. TMDXIDK5728 Hardware Setup¶

Description

The TMDXIDK5728 is a standalone test, development, and evaluation module system that enables developers to write software and develop hardware for industrial communication type applications. It has been equipped with a TI AM572x processor and a defined set of features to allow the user to experience industrial communication solutions using serial or Ethernet based interfaces. Using standard interfaces, the IDK may interface to other processors or systems and act as a communication gateway in this case. In addition it can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows emulation and debug using standard development tools such as TI’s Code Composer Studio by just using the supplied USB cable.

EVM Layout and key components

• PRU1ETH0 and PRU2ETH0 are not enabled by default

Quick Start Guide

This section talks about how to quickly setup the AM572x Industrial Development Kit (IDK) EVM. This guide is a Beta version and it is designed to help you through the initial setup of the EVM.

1. Once you have received the TI-RTOS or Linux™ software from your TI representative, create a bootable µSD card (using the included blank µSD) and insert it into the EVM

2. Connect the power cable to the power jack on the board and plug in to an AC power source

Note: When powering this IDK, always use the recommended power supply (GlobTek Part Number TR9CA6500LCP-N, Model Number GT-43008-3306-1.0-T3) or equivalent model having output voltage of +5VDC and output current max 6.5 Amp as well as the applicable regional product regulatory/safety certification requirements requirements such as (by example) UL, CSA, VDE, CCC, PSE, etc.

3. Connect the microUSB cable to USB JTAG/Console port on the EVM and connect to the USB on the host. Connect Ethernet cable to GIG ETH0 if Network connectivity is required

Note: The serial port will not show up on the host PC until you power on the EVM.

4. Select the power ON button to run power the IDK.

After, you power on the EVM the Status, Industrial LED2, Industrial LED3 will turn on. If the microUSB cable is pluged in then the LED corresponding to FTDI UARTtoUSB will be turned on.

5. Users can now connect to UART and the on board XDS100 emulator from the host machine.For UART port connections set the serial terminal software Tera term/minicom/hyperterminal to baudrate 115200 to see log messages. Connecting to target using emulator has been discussed in the section below.

Connecting IDK EVM to Code Composer Studio

Step1 : Download Code composer Studio and AM572x Sitara CSP package as described in the wiki article mentioned below:

Install Code composer Studio for AM572x

Step2: Connect IDK EVM as described in the Quick Start Guide. Populating the uSD card is not required as the intent is to connect and load code over emulator and not to boot the device using uSD card. AM572x IDK doesn`t have any boot switches to configure for emulation mode.

Step3: Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below and provide appropriate name to the configuration. Select Texas Instuments XDS100v2 emulator and target as IDK_AM572x.

• Cortex_A15_0: ..\..\emulation\boards\am572x\gel\idk_am572x.gel
• C66x_DSP1: ..\..\emulation\boards\am572x\gel\AM572x_dsp_startup.gel
• Cortex_M4_IPU1_C0: ..\..\emulation\boards\am572x\gel\AM572x_cortexM4_startup.gel

Note: GEL files are located under ccsv6\ccs_base\emulation\boards\am572x\gel after the CSP package is installed

CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output:    Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output:    Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output:    PER DPLL already locked, now unlocking
CortexA15_0: GEL Output:    PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    CORE DPLL OPP  already locked, now unlocking....
CortexA15_0: GEL Output:    CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output:    ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output:    PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output:    PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output:    DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output:    DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output: DEBUG: Overall DDR configuration
CortexA15_0: GEL Output: DEBUG: EMIF1 and EMIF1 DDR IOs config (CTRL_MODULE_CORE_PAD module)
CortexA15_0: GEL Output: DEBUG: DDR PHY config (CTRL_MODULE_WKUP module)
CortexA15_0: GEL Output: DEBUG: EMIF1 ctrl + associated DDR PHYs initial config (EMIF1 module)
CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling
CortexA15_0: GEL Output: DEBUG: EMIF2 ctrl + associated DDR PHYs initial config (EMIF2 module)
CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling
CortexA15_0: GEL Output: DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<

Step6 : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts menu and under AM572x MULTICORE Initialization enable the corresponding Sub system clock Enable API.For Eg. FOr DSP1 select DSP11SSClkEnable_API. After running the clock enable option, you can connect to the core.

Related Links

AM572x_Industrial_EVM_Hardware_Users_Guide

6.3.3. 66AK2GX GP EVM Hardware Setup¶

Description

The EVMK2G is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop applications for the Texas Instrument’s Keystone2 System-on-Chip (SoC) 66AK2GX. The Key features of EVM are:

Processor and controller

• K2G SoC 66AK2GX is based on keystone II architecture with ARM cortex A15 @600MHz and C66x DSP @600MHz
• Board Management Controller (BMC) for board management functions like system status and Boot mode control

Volatile and non volatile Memory/Interfaces:

• 2GByte of DDR3L with ECC
• 2Gbit of NAND Flash
• 128Mbit of SPI Flash
• 512Mbit of QSPI Flash
• 128kByte of I2C EEPROM for Boot support from I2C
• Micro SD-Card slot
• 16GByte of eMMC

High speed and Serial Interfaces

• Gigabit Ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connector
• PCIe x1 card slot
• COM8 interface
• DCAN and MLB interfaces
• One USB2.0 host and one USB2.0 Dual-role ports
• One RS232 serial interface on DB9 connector or UART over mini-USB connector, One UART interface on 6 pin header

Multimedia and display:

• 4.3” LCD display with Capacitive touch (Sold separately)
• HDMI transmitter
• Audio Line In and Line Out

JTAG and Emulation:

• MIPI 60-Pin JTAG header to support all types of external emulator
• On Board XDS200 Emulator
• Powered by DC power-wall adaptor (12V/5A)

EVM Layout and Key Components

JTAG debug probes (aka Emulators) supported

List of standalone JTAG debug probes supported:

• XDS100-class JTAG debug probes (low cost, low performance). XDS100v1 is not supported.
• XDS200-class JTAG debug probes (recommended)
• XDS560v2-class JTAG debug probes (high performance)

Minimal EVM setup

Setting boot switches

The DIP Switch /Boot mode switch (SW3) is used for selecting the boot mode.

Note: Read the PCB marking around the boot switch for your EVM to interpret of ON and OFF marking on the switch

• For Rev C K2G02 GP EVM: ON = ‘0’ and OFF = ‘1’
• For Rev C/Rev D K2G12 GP EVM: ON = ‘1’ and OFF = ‘0’

Other Boot Pin configurations:

Connecting Emulator

Note: This EVM setup is only required for developers who need to connect to cores using Code Composer studio to load application.

When external emulator is not connected to MIPI 60-pin connector, On-board XDS200 embedded JTAG emulator is the default type of emulation (SoC JTAG signals are routed to XDS200 on-board emulator). When external emulator is connected to MIPI 60-pin header, it is automatically detected and SoC JTAG signals are routed to external emulator.

On Board XDS200 emulator

EVMK2G has on-board XDS200 embedded JTAG emulation circuitry. Hence user does not require any external emulator to connect EVM with Code Composer Studio (CCS). User can connect target SoC in EVM to CCS through USB cable supplied in the EVM kit.

Use the USB to USB mini-B cable provided. Connect the USB mini-B connector to the USB mini-B interface near to the audio line in on the EVM, and the USB connector to your PC. This enables XDS-2xx emulation and is directly useable by CCS.

If you are using a different JTAG, you can connect it at MIPI60 connector (EMU1). The MIPI 60-pin JTAG header is provided on-board for high speed real-time emulation. All JTAG and EMUxx signals are terminated on MIPI 60-pin header.

No emulation firmware upgrade is required if users plan to use an external emulator The MIPI 60-pin JTAG header supports all standard (XDS510 or XDS560) TI DSP emulators. Please refer to the documentation supplied with your emulator for connection assistance.

Powering up the EVM

Power Supply specifications

The EVMK2G can be powered from a single +12V / 5.0A DC (60W) external power supply connected to the DC power jack (J3). Internally, +12V input is converted into required voltage levels using local DC-DC converters

Please note that a power supply is included with the 66AK2GX Evaluation Module. The power supply has the following specs :

• 12V DC output
• 5A output
• Positive inner and negative outer terminals
• Female barrel with 2.5mm inner diameter and 5.5mm outer diameter
• Isolated power supply

CCS Setup

This section describes the setup to connect to 66AK2GX GP EVM using Code composer Studio environment and an emulator.

There are two scenarios while connecting to the EVM :

• Connect to EVM without a SD card boot image to boot the EVM
• Connect to EVM after booting an image from the SD card.

Before discussing both these scenarios, let us look at how to pull in the latest KeystoneII device support in CCSv6

Update CCS v6 to install Keystone II device Support package

All revisions of the board require this step to be performed in order to get the latest GEL files and the target content for the K2G. This step will not be required for CCS versions higher than version 6.1.3. CCSv6.1.3 package contain KeystoneII device support package v1.1.4 which doesn`t contain 66AK2GX GPEVM specific target files hence we recommend this update.

Step 1 All CCS v6.1.3 and earlier version users are required to update the Keystone Device Support package by going into the Help->Check For Updates

Step 2 Select Keystone2 device support package. Follow menu options to continue with the update

Step 3 After the update is complete go to Help->Installation details and check that Keystone2 device support package v1.1.5 or later are installed as shown below

Note: The package can be downloaded separately from the link below and manually unzipped into CCSv6 installation.

• Device Support Files

Connect without a SD card boot image

Configuring target configuration files

Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below

Note: If you don`t find the 66AK2G02 target make sure you have installed the CCSv6.1.3 package or for CCSv6.1.2 and earlier ensure that you have done the software update correctly as shown in the how to section below.

In advance settings, make sure that the gel files are populated correctly. The following GEL files and their corresponding cores are provided below:

• C66X Core: evmk2g.gel
• A15 Core: evmk2g_arm.gel

Connecting to target

Step1 : Download Code composer Studio v6.1.3 or for CCSv6.1.2 and earlier, ensure it contains Keystone device support package version 1.1.5 as described in the how to guide

Install Code composer Studio v6 for K2G

Step3: Connect an XDS200 Emulator to XDS USB of the GP EVM as shown in section.Connecting_Emulator

Step4: Launch CCS and create new target configuration as discussed in the previous section.

GEL Log

A15_0: GEL Output: PLL has been configured (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
A15_0: GEL Output: ARM PLL has been configured with ref clock 24MHz, -sysclkp_period 41.6666 (24.0 MHz * 100 / 1 / 4 = 600.0 MHz)
A15_0: GEL Output: Power on all PSC modules and DSP domains...
A15_0: GEL Output: Power on PCIE PSC modules and DSP domains... Done.
A15_0: GEL Output: UART PLL has been configured (24.0 MHz * 128 / 1 / 8 = 384.0 MHz)
A15_0: GEL Output: NSS PLL has been configured (24.0 MHz * 250 / 3 / 2 = 1000.0 MHz)
A15_0: GEL Output: ICSS PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz)
A15_0: GEL Output: DSS PLL has been configured (24.0 MHz * 198 / 12 / 16 = 24.75 MHz)
A15_0: GEL Output: DDR PLL has been configured (24.0 MHz * 250 / 3 / 10 = 200.0 MHz)
A15_0: GEL Output: XMC setup complete. A15_0: GEL Output: DDR3 PLL Setup ...
A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.
A15_0: GEL Output: DDR3A initialization complete

Connect with a SD card boot image

Launch CCS and create new target configuration(File->New->Target Configuration file) as shown in the images below

Note: If you don`t find the 66AK2G02 target make sure you have installed the CCSv6.1.3 package or for CCSv6.1.2 and earlier ensure that you have done the software update correctly as shown in the how to section below.

In advance settings, make sure that the no gel files are populated.

Step3: Connect an XDS200 Emulator to XDS USB of the GP EVM as shown in section.Connecting_Emulator

Step4: Launch CCS and create new target configuration as discussed in the previous section.

Step7 SD card boot image will typically load a secondary bootloader like u-boot that will put the DSP in reset so user will need to follow the instructions on wiki that talks about Taking DSP out of reset

Note: RTOS users don`t need to follow this step as the Secondary bootloader (SBL) will put the DSP in idle state and not in reset if there is no code running on the DSP.

How to guide

This section guides users who are using older versions of the GP EVM which may require an update to the firmware flashed on the EVM or hardware updates to workaround specific issues. Each section specifies the affected versions and the fix for the issue.

Create SD card to boot Linux on the GP EVM

All pre-production boards (Rev C and earlier) will not contain a SD card image in the kit without an image flashed on it for the Out of Box experience described in the Quick start guide. User are required to download the image seperately from the Processor SDK Linux portal and run a script to create the SD boot image. The steps to create the image are provided below:

Step 1 Download the image k2g-evm-linux-xx.xx.xx.xx.img.zip from the link Latest Processor SDK Linux

Step 2 Follow instructions to create a SD card for the EVM using the instruction in the SD card creation wiki

Update the BMC firmware on the EVM

The section describes how the Board Management controller firmware on the board can be updated through the BMC UART interface. All boards prior to RevC, require a BMC update for the following issue:

• CDCM chip on the board generates clocks to modules like PCIe and USB. It is possible to use PCIe only in external clock mode on the EVM. However there can be use-cases where PCIe clock should be enabled with SoC running in internal clock mode.

• LMflashProgrammer tool

Step 3 Connect the mini USB cable between host PC and ‘USB to SoC UART0’ port (J23) on EVM

Step 4 Remove the jumper J10 and power on the K2G EVM

Step 5 Open the LM Flash programmer utility on the windows host machine.

Step 6 In the LM Flash Programmer Utility ‘Configuration’ tab, in the interface section, select ‘Serial (UART)’ from the drop-down box on the left.Refer to the image provided below:

Step 7 Select the BMC COM Port and set the ‘Baud Rate’ to 115200.

• There will be two COM ports that appears on EVMs ‘USB to SoC UART0’ port. Select the one which is connected to BMC. To find which port corresponds to the BMC, you can open a serial terminal program or Device Manager on your PC and check the port number corresponding to “Silicon Labs CP210x: USB to UART Bridge: Standard COM Port (COM##)” as shown below:

Note: BMC outputs boot logs to serial console when EVM is powered ON. Connect the ‘USB to SoC UART0’ port to standard serial console application to find the right COM port that is connected to BMC.

Step 8 Set ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’ is unchecked.

Step 9 In the ‘Program’ tab, select the binary image file bmc_evmKS2_K2G.bin in the section ‘Select.bin file’.

Step 10 Leave all other options as default, and press the ‘Program’ button.

Step 11 Wait till ‘Program Complete’ status in the status bar.

Step 12 Connect the jumper J10 and reboot the EVM

Update XDS200 firmware and hardware components on the GP EVM

Note: This update is only required if you are using the on board XDS200 debug probe.

The RevB and RevC boards are using an earlier version of the XDS200 firmware. We have observed the following issues when hooking up the internal XDS200 USB debug probe to a host machine.

• XDS200 Emulator USB cable need to be re-plugged every time board is power cycled/reset to avoid leakage on power supply VCC1V8_XDS which can damage the regulator or other ICs

Workaround for this issue

• Use external emulators with the MIPI 60 adapter included int he kit.
• Perform following firmware and hardware updates to the GP EVM (RevC and earlier)

Software Update Required

Steps to update the XDS200 firmware on the EVM are archived on the wiki article Updating_the_XDS200_firmware

Hardware updates required

• Replace R431 & R442 to 200E
• Mount resistors R95, R107, R108, R115.
• Mount D2, R600, R599 components.
• Remove FB3 and connect a wire from R64.2 ‘rVCC_VBUS_XDS’ and R67.2 ‘VCC5V0_DCDC’ as shown in the image below:

Update the EVM for improved USB performance

The external resistors for the USB (R442 and R431) are currently 10k Ω. We recommend that users need to replace these with 200 Ω / 1%.

Useful Resources and Support

• 66AK2G02 Product folder
• 66AK2G12 Product folder
• 66AK2Gx GP EVM Technical Reference Manual
• 66AK2Gx GP EVM Product folder
• 66AK2Gx 1GHz GP EVM Product folder
• Keystone E2E Support Forum