APIs for SDL ECC

Introduction

This Header file contains enumerations, structure definitions and function declarations for SDL ECC interface.

Sub Modules
	ECC_AGGR Data Structures
	ECC_AGGR Enumerated Data Types
	ECC_AGGR Functions
	ECC_AGGR Macros

Files
file	sdl_ecc.h
	Header file contains enumerations, structure definitions and function.
file	sdl_ecc_soc.h
	Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable.

Typedefs
typedef void(*	SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address)
typedef void(*	SDL_ECC_VIMDEDVector_t) (void)

Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (6U)
#define	SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)
#define	SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (12U)
#define	SDL_CPSW0_ECC_U_BASE   (SDL_CPSW0_U_BASE + 0x3f000u)
#define	SDL_OSPI_ECC_U_BASE   (0x53807000u)
#define	SDL_FOTA_ECC_U_BASE   (0x5380F000u)
#define	SDL_R5FSS0_CORE0_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS)
#define	SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
#define	SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE)
#define	SDL_R5FSS0_CORE1_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS)
#define	SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
#define	SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_CTRL)
#define	SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_STATUS)
#define	SDL_TPCC0_ERRAGG_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_STATUS)
#define	SDL_TPCC0_ERRAGG_MASK   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_MASK)
#define	SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL)
#define	SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL)
#define	SDL_TMU0_ROM_PARITY_EN   (0x1U)
#define	SDL_TMU0_ROM_PARITY_FORCE_ERR   (0x2U)
#define	SDL_TMU0_ROM_PARITY_ERR_CLR   (0x10000U)
#define	SDL_PARAM_REG_1   (SDL_PARAM_REG_SET0 + 0x20U)
#define	SDL_PARAM_REG_2   (SDL_PARAM_REG_SET0 + 0x30U)

Macro Definition Documentation

SDL_ECC_WIDTH_UNDEFINED

#define SDL_ECC_WIDTH_UNDEFINED   0x1

SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (6U)

SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)

SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)

SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)

SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES   (12U)

SDL_CPSW0_ECC_U_BASE

#define SDL_CPSW0_ECC_U_BASE   (SDL_CPSW0_U_BASE + 0x3f000u)

SDL_OSPI_ECC_U_BASE

#define SDL_OSPI_ECC_U_BASE   (0x53807000u)

SDL_FOTA_ECC_U_BASE

#define SDL_FOTA_ECC_U_BASE   (0x5380F000u)

SDL_R5FSS0_CORE0_TCM_ERR_STATUS

#define SDL_R5FSS0_CORE0_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS)

SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW

#define SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)

SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE

#define SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE)

SDL_R5FSS0_CORE1_TCM_ERR_STATUS

#define SDL_R5FSS0_CORE1_TCM_ERR_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS)

SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW

#define SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)

SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL

#define SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_CTRL)

SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS

#define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_STATUS)

SDL_TPCC0_ERRAGG_STATUS

#define SDL_TPCC0_ERRAGG_STATUS   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_STATUS)

SDL_TPCC0_ERRAGG_MASK

#define SDL_TPCC0_ERRAGG_MASK   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_MASK)

SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL

#define SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL)

SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL

#define SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL   (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL)

SDL_TMU0_ROM_PARITY_EN

#define SDL_TMU0_ROM_PARITY_EN   (0x1U)

SDL_TMU0_ROM_PARITY_FORCE_ERR

#define SDL_TMU0_ROM_PARITY_FORCE_ERR   (0x2U)

SDL_TMU0_ROM_PARITY_ERR_CLR

#define SDL_TMU0_ROM_PARITY_ERR_CLR   (0x10000U)

SDL_PARAM_REG_1

#define SDL_PARAM_REG_1   (SDL_PARAM_REG_SET0 + 0x20U)

SDL_PARAM_REG_2

#define SDL_PARAM_REG_2   (SDL_PARAM_REG_SET0 + 0x30U)

Typedef Documentation

SDL_ECC_ErrorCallback_t

typedef void(* SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address)

/brief Format of ECC error Call back function

SDL_ECC_VIMDEDVector_t

typedef void(* SDL_ECC_VIMDEDVector_t) (void)

/brief Format of VIM DED vector function

Variable Documentation

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_SOC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
      SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0u,
      SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
    { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0u,
      SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 8u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_SOC_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE1_ECC_AGGR

SDL_HSM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_HSM_ECC_AGGR

SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48000000u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48002000u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48034000u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48038000u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48010000u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR

SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48600000u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48602000u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48634000u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48638000u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48610000u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_CPSW3GCSS_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x5283E000u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x52832000u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW3GCSS_ECC_AGGR

SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries[SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID, 0x53807000u,
      SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_SIZE, 4u,
      SDL_FSS_OSPI_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS_OSPI_RAM_ECC_AGGR

SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID, 0x5380f000u,
      SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_SIZE, 4u,
      SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype [SDL_FSS_FOTA_8051_RAM_ECC_AGGR

SDL_OSPI1_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_OSPI1_RAM_ECC_AGGR_MemEntries[SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_OSPI1_RAM_ECC_AGGR_RAM_ID, 0x53807000u,
      SDL_OSPI1_RAM_ECC_AGGR_RAM_SIZE, 4u,
      SDL_OSPI1_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_OSPI1_RAM_ECC_AGGR

SDL_SOC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SOC_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE1_ECC_AGGR

SDL_HSM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_HSM_ECC_AGGR

SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR

SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_CPSW3GCSS_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW3GCSS_ECC_AGGR

SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable[SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID,
      SDL_FSS_OSPI_RAM_ECC_AGGR_INJECT_TYPE,
      SDL_FSS_OSPI_RAM_ECC_AGGR_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS_FOTA_8051_RAM_ECC_AGGR

SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID,
      SDL_FSS_FOTA_8051_RAM_ECC_AGGR_INJECT_TYPE,
      SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS_FOTA_8051_RAM_ECC_AGGR

SDL_OSPI1_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_OSPI1_RAM_ECC_AGGR_RamIdTable[SDL_OSPI1_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_OSPI1_RAM_ECC_AGGR_RAM_ID,
      SDL_OSPI1_RAM_ECC_AGGR_INJECT_TYPE,
      SDL_OSPI1_RAM_ECC_AGGR_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS_FOTA_8051_RAM_ECC_AGGR

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]

static

Initial value:

=
{
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM1_ECC_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
      ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_U_BASE)),
      ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_OSPI_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FOTA_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS_UL_128_FSS_OF_UL_OSPI0_OSPI_CFG_VBUSP_OSPI_WRAP_ECC_AGG_VBP_U_BASE)),
}

SDL_ECC_aggrTransBaseAddressTable

SDL_ecc_aggrRegs* SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static