AM243x Motor Control SDK  11.00.00
Tamagawa

Table of Contents

Introduction

The Tamagawa receiver firmware running on PRU-ICSS provides a well-defined interface to execute the Tamagawa encoder communication protocol. The Tamagawa diagnostic application interacts with the Tamagawa receiver firmware interface.

Note
This implementation using Peripheral input/output mode of PRU-ICSS. Refer Peripheral IF mode for more details.

Features Supported

  • Supports full-absolute SmartAbs & SmartInc encoders compatible with Smartceiver AU5561N1
  • Channel selection
  • Baud rate selection
  • Supports all Data Readout, Reset and EEPROM commands
  • Support for concurrent multi-channel support on a single PRU (up to 3 identical encoders)
    • In this mode, data transmission and reception must happen simultaneously on all channels.
    • The encoder configuration and cable length should be the same on all channels.
    • If encoders across channels don't respond at the same time, this mode will not work.
  • 2.5 Mbps and 5 Mbps encoder support
    Note
    In three channel interface of PRU-ICSS, receive (Rx) is oversampled at 8x of send (Tx). Therefore, the encoder interface frequency "f" should be such that Tx source clock value is divisible by "f" and Rx source clock value is divisible by "(8*f)".
  • Possible interface speeds with different source clock combinations.
    Clock Source

    Interface Speed

    PRU Core Clock (200 MHz)

    2.5 MHz, 5 MHz

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the following:

  • Other baud rates.

SysConfig Features

Note
It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure the following:

  • Selecting the ICSSG instance
  • Selecting the ICSSG PRU slice (Tested on ICSSG0-PRU1)
  • Configuring PINMUX, GPIO and ICSS clock to 200 MHz
  • Enabling SA Mux mode
  • Channel selection
  • Baud rate selection
  • Selecting RX and TX source clock

ICSS PRU Resource Usage

Configuration PRU Core Memory Usage IEP Usage Other Peripheral Usage Description
Single channel PRUx DMEM: 220 Bytes, from offset 0x00 to 0xDC offset
IMEM: 1.8 KB 		IEP0: CMP0 and CMP3 INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to Arm® Cortex®-R5F

IEP, CMP events and INTC signal are used only in periodic continuous mode

Multi-channel with single PRU core PRUx DMEM: 220 Bytes, from offset 0x00 to 0xDC offset
IMEM: 1.5 KB 		IEP0: CMP0 and CMP3 INTC event/input number 18 (pr[0/1]_pru_mst_intr[2]_intr_req) is used to trigger interrupt to R5F

IEP, CMP events and INTC signal are used only in periodic continuous mode

Note
For pin usage, see Pin Multiplexing section.

Tamagawa Design

Tamagawa Protocol Design explains the design in detail.

Example

API

APIs for Tamagawa Encoder

Note
Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.