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AM243x Motor Control SDK
2025.00.00
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AM243x Motor Control SDK
2025.00.00
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This document presents the firmware implementation details of the Tamagawa receiver protocol.
It is an encoder technology used for obtaining high-precision position information in machine tools, robotics, and so forth. Tamagawa rotary encoders consist broadly of two types: incremental or absolute. Incremental encoders provide a train of pulses, while the absolute-type provides digital values. The absolute encoder group contains the single-turn types that provide outputs which can be open collector or emitter follower. The absolute encoder types include the pure digital encoder types, which provide a digital word output through a line driver such as an RS485, or a semi-absolute encoder, which provides both digital word and pulse train outputs. Of the RS485 line-driver output absolute encoders that provide only digital output, another classification is the full absolute encoder. A full absolute encoder provides multi-turn digital data, which is known as SmartAbs, and is compatible with the Tamagawa Smartceiver AU5561N1. Another type of encoders, known as SmartInc, provide single-turn information in digital format with an RS485 line driver output. The AM243X Tamagawa receiver implementation is equivalent to the Smartceiver AU5561N1, which can communicate with Tamagawa SmartAbs as well as SmartInc encoders.
The AM243X Tamagawa receiver communicates with Tamagawa SmartAbs and SmartInc encoders and provides drive control with digital information to and from the encoder. Tamagawa communication is broadly classified into three types: data readout, reset, and EEPROM transactions. Four data readout transactions occur: absolute data in one revolution, multi-turn data, encoder ID, and a combination of all of these along with the encoder error status. The reset transaction always returns the absolute data in one revolution while performing different types of resets. Three types of reset are available: reset of absolute data in one revolution, reset of multi-turn data, and error reset. The EEPROM transaction allows the system to read and write to the EEPROM in the encoder. Each transaction has a unique data ID and consists of different fields, namely control, status, data, cyclic redundancy check (CRC), EEPROM address, and EEPROM data depending on the type of transaction, that is, data ID.
Each field is 10-bits long, beginning with a start bit and ending with a delimiter. The 8 bits between these start bits and delimiters depend on the field type. The control field contains the data ID information. Data, status, and CRC fields similarly contain data, status, and CRC in those 8 bits. The receiver initially sends the control field to start the communication. This action indicates the type of transaction to the encoder and the encoder returns this information based on the data ID, as the previous paragraph explains. The encoder always returns the control field back to the receiver. In the case of data readout and reset transactions, the encoder returns the control field followed by the status, data, and ending with the CRC field at the end. In the case of an EEPROM read or write, the receiver, in addition to the control field, sends the EEPROM address field (and EEPROM data field for write) followed by the CRC. The encoder returns the control field, followed by the EEPROM address, EEPROM data, and CRC fields. The physical layer communication is RS422/RS485 based.
Refer to TRM for details
Refer to PRU-ICSS chapter of AM243X Technical Reference Manual
At start-up, the application running on the Arm®-based core initializes the module clocks and configures the pinmux. The PRU is initialized and the PRU firmware is loaded on PRU slice of choice for a chosen ICSS instance (tested on PRU1 on ICSSG0).
After the PRU starts executing, the Tamagawa interface is operational and the application can use it to communicate with an encoder. Use the Tamagawa diagnostic example to learn more about initialization and communication with the Tamagawa interface. This Tamagawa diagnostic example also provides an easy way to validate the Tamagawa transactions. The diagnostic example provides menu options on the host PC in a serial terminal application, where the user can select the data ID code to be sent. Based on the data ID code, the application updates the Tamagawa interface with the data ID code and triggers transaction. The application then waits until it receives an indication of complete transaction by the firmware through the interface before displaying the result.
Deterministic behavior of the 32 bit RISC core running up to 333 MHz provides resolution on sampling external signals and generating external signals. It makes use of 3 channel peripheral interface support in PRU for data transmission/reception.
The PRU-ICSS firmware supports the following configurations:
The firmware first initializes the PRU hardware. Then it checks the operation mode: host trigger mode, periodic CMP mode, or periodic CAP mode.
Then it checks the operation mode: host trigger mode, periodic CMP mode, or periodic CAP mode.
Host Trigger Mode: The firmware waits until a command has been triggered through the interface by the host application.
Periodic CMP Mode (Compare Event Mode): In CMP mode, IEP timer compare event triggers position sampling. The firmware monitors the configured IEP compare event and automatically initiates Tamagawa transactions when the IEP timer counter matches the compare value. This enables fixed-rate periodic sampling.
Periodic CAP Mode (Capture Event Mode): In CAP mode, external signals trigger position sampling through IEP capture events. The capture event is triggered on the rising edge of the external input pulse, enabling event-driven position capture. Internal signals can also be mapped to IEP capture events via TIMESYNC/GPIOMUX router. The following is the operation flow for the periodic mode:
Upon triggering (from any mode), the transmit data is set up based on the data ID code and the data is transmitted. The data ID code then waits until receiving all the data that depends on the data ID. The parsing over the received data then commences, which is again based on the data ID, and the interface is updated with the result. The CRC verification occurs next and the interface indicates command completion. The firmware then waits for the next command trigger from the interface or IEP compare/capture event.
PRU is set to 3 channel peripheral interface first. The entire Tamagawa configuration MMRs are cleared (CFG registers). Tx global reinit bit in R31 is set to put all channels in default mode. The clock source is selected. In Tx mode, the output data is read from the Tx FIFO at this 1x clock rate. In Rx mode, the input data is sampled at the Oversampling (OS) clock rate. Hence, Tx clock (1x clock) and Rx clock (Oversampling (OS) clock) are set up by selecting oversampling factor (x8). At the end of the initialization, status is updated and waits until trigger from user occurs for Tamagawa commands.
The transmit and receive sizes are determined based on the data ID in the interface.
In the current implementation, the Transmit data is loaded into the Tx FIFO byte-wise. For data readout and reset commands, the requirement is to send 1 frame of 10 bits. So, 2 bytes of data are first loaded into the Tx FIFO and Tx frame size is set to 10 bits to send right data to encoder. Similarly, for EEPROM Read command, the requirement is to send 3 frames of 10 bits each, so 30 bits in total. For this, 4 bytes of data are first loaded into the Tx FIFO and then Tx frame size is set to 30 bits to send right data to encoder. This is done by using the Tx - Single Shot mode.
In case of EEPROM Write command, the requirement is to send 4 frames of 10 bits each - 40 bits in total. For this, 4 bytes of data are first loaded into the Tx FIFO and then transmission is started in Tx - Continuous FIFO loading mode. FIFO byte level is constantly monitored and the FIFO is reloaded with the last byte when the FIFO level reaches 3 bytes.
Once the transmission is complete, the encoder starts sending the data and the firmware copies the receive FIFO contents onto the receive buffer, individually, until all the data has been received.
Depending on the data ID used for initiating the transfer, the firmware parses the received data and copies it onto relevant fields in the interface, accordingly.
The CRC is the last byte of the received data. The firmware then calculates the CRC of the received data excluding the last byte, compares it with the received CRC value, and updates the CRC status in the interface.
| Pin name | Signal name | Function |
|---|---|---|
| PRG<k>_PRU<n>_GPO0 | pru<n>_tamagawa0_clk | Channel 0 clock |
| PRG<k>_PRU<n>_GPO1 | pru<n>_tamagawa0_out | Channel 0 transmit |
| PRG<k>_PRU<n>_GPO2 | pru<n>_tamagawa0_out_en | Channel 0 transmit enable |
| PRG<k>_PRU<n>_GPI13/PRG<k>_PRU<n>_GPI9 | pru<n>_tamagawa0_in | Channel 0 receive |
| PRG<k>_PRU<n>_GPO3 | pru<n>_tamagawa1_clk | Channel 1 clock |
| PRG<k>_PRU<n>_GPO4 | pru<n>_tamagawa1_out | Channel 1 transmit |
| PRG<k>_PRU<n>_GPO5 | pru<n>_tamagawa1_out_en | Channel 1 transmit enable |
| PRG<k>_PRU<n>_GPI14/PRG<k>_PRU<n>_GPI10 | pru<n>_tamagawa1_in | Channel 1 receive |
| PRG<k>_PRU<n>_GPO6 | pru<n>_tamagawa2_clk | Channel 2 clock |
| PRG<k>_PRU<n>_GPO12/PRG<k>_PRU<n>_GPO7 | pru<n>_tamagawa2_out | Channel 2 transmit |
| PRG<k>_PRU<n>_GPO8 | pru<n>_tamagawa2_out_en | Channel 2 transmit enable |
| PRG<k>_PRU<n>_GPI11 | pru<n>_tamagawa2_in | Channel 2 receive |
| Pin name | Signal name | Function |
|---|---|---|
| PRG0_PRU1_GPO0 | pru1_tamagawa0_clk | PRU1 Channel 0 clock |
| PRG0_PRU1_GPO1 | pru1_tamagawa0_out | PRU1 Channel 0 transmit |
| PRG0_PRU1_GPO2 | pru1_tamagawa0_out_en | PRU1 Channel 0 transmit enable |
| PRG0_PRU1_GPI13 | pru1_tamagawa0_in | PRU1 Channel 0 receive when SA mux selection is enabled (ICSSG_SA_MX_REG[7] G_MUX_EN = 1) |
| PRG0_PRU1_GPO6 | pru1_tamagawa2_clk | PRU1 Channel 2 clock |
| PRG0_PRU1_GPO12 | pru1_tamagawa2_out | PRU1 Channel 2 transmit when SA mux selection is enabled (ICSSG_SA_MX_REG[7] G_MUX_EN = 1) |
| PRG0_PRU1_GPO8 | pru1_tamagawa2_out_en | PRU1 Channel 2 transmit enable |
| PRG0_PRU1_GPI11 | pru1_tamagawa2_in | PRU1 Channel 2 receive |
| GPIO Pin (GPIO1_78/C16) | ENC0_EN | Enable encoder voltage in Axis 1 of BP (Fix this pin to high with SoC GPIO mode) |
| GPIO Pin (GPIO1_77/B17) | ENC2_EN | Enable encoder voltage in Axis 2 of BP (Fix this pin to high with SoC GPIO mode) |
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