SDFM Example With Phase Compensation

Table of Contents

• ICSS SDFM three channel with phase compensation
• Important files and directory structure
• Supported Combinations
• Steps to Run the Example
  • Hardware Prerequisites for EVM
    • EVM Hardware Setup
  • Hardware Prerequisites for LP
    • LP Hardware Setup
  • Build, load and run
    • Test Case Description

ICSS SDFM three channel with phase compensation

This example demonstrates phase compensation implemented for channel 0. It uses PRU-ICSSG IEP SYNC0 and SYNC1 to generate phase delayed clock for SDFM interface and modulator.

It measures the phase delay for SDFM channel 0 in PRU GPIO mode during initialization. Normal current Over-sampling Ratio (OSR), Over current OSR and Normal current trigger time can be configured by the user.

Note: The current firmware supports measuring the phase delay using the SD0_DATA pin and the SD8_CLK pin for a single-axis use case. A similar measurement can be applied and implemented for multi-axis or individual channels as described in Data/Clock Phase Compensation.

This example demonstrates a three-channel single PRU configuration that performs the following tasks:

• Configures ICSSG0 IEP0 to generate a clock for the SDFM interface and modulator.
• Enables phase compensation measurement.
• Configures the SYNC1 delay register based on the measured phase delay.
• Sets up SDFM channels: Channel 0, Channel 1 and Channel 2.
• Configures the normal current sample trigger time, oversampling ratio (OSR), and sinc filter type.

Important files and directory structure

Folder/Files	Description
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation	Application specific sources for ICSS SDFM with phase compensation
${SDK_INSTALL_PATH}/examples/current_sense	Common source for ICSS SDFM applications
${SDK_INSTALL_PATH}/source/current_sense/sdfm
firmware/	Folder containing ICSS SDFM firmware sources
driver/	ICSS SDFM driver source
include/	Folder containing ICSS SDFM structures and APIs declarations

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 freertos
ICSSG	ICSSG0
PRU	PRU0
Toolchain	ti-arm-clang
Board	am243x-evm, am243x-lp
Examples folder	examples/current_sense

Steps to Run the Example

Hardware Prerequisites for EVM

Other than the basic EVM setup mentioned in EVM Setup , the additional hardware listed below is required to run this demo

• TMDS64DC01EVM IO Link/Breakout Board
• AMC1035EVM
• TMDS243EVM
• Signal generator

EVM Hardware Setup

Hardware Setup SDFM

SDFM: EVM and IO breakout board setup view

Hardware Prerequisites for LP

• AMC1035EVM
• LP-AM243 Board
• Signal generator

LP Hardware Setup

LP Hardware setup

SDFM: LP setup view

Build, load and run

• When using CCS projects to build, import the CCS project and build it using the CCS project menu (see Using SDK with CCS Projects ).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

Test Case Description

Test Details	Steps	Pass/Fail Criteria
1. To check Phase Compensation	1. Run the example on supported board
	2. Probe ch0 SD0_D pin and SD8_CLK pin
	3. Build and run example
	4. Take timestamp of any rising edge of SD0_D pin and upcoming active SD8_CLK edge
	5. Compare this time with measured delay (stored in DMEM at offset 0x18)	Both values should be the same or have a maximum variation of 1 PRU cycle