Basic ICSS SDFM Examples

Table of Contents

• Three Channels
• Nine Channels
• Important files and directory structure
• Supported Combinations
• Steps to Run the Example
  • Hardware Prerequisites for EVM
    • EVM Hardware Setup
  • Hardware Prerequisites for LP
    • LP Hardware Setup
  • Build, load and run
    • Test Case Description

These examples demonstrate both trigger-based and continuous normal current sampling. The examples support Normal Current, Over Current, and Fast Detect configurations.

There are three different examples based on the number of SDFM channels and the mode of Normal Current sampling.

Note: Normal Current trigger mode examples do not support Over Current.

Three Channels

Only one core, PRU, is used for these examples.

1. Continuous Mode Example
   
   • Continuous Normal Current sampling.
     
   • Three channels: Channel 0, Channel 1, and Channel 2.
     
   • Each channel has an individual interrupt to Arm® Cortex®-R5F.
     
   • ICSS PWM trip-based Fast Detect. ICSS PWM0 instance is used to generate the PWM trip.
     
   • ICSS PWM trip-based Over Current detection. ICSS PWM0 instance is used to generate the PWM trip.
     
     • Note: Over Current OSR should be equal to Normal Current OSR.
       
2. Trigger Mode Example
   
   • Three channels: Channel 0, Channel 1, and Channel 2.
     
   • Trigger-based Normal Current sampling synchronized with EPWM.
     
   • A common interrupt is used for all three channels.
     
   • ICSS PWM trip-based Fast Detect. ICSS PWM0 instance is used to generate the PWM trip.
     

Nine Channels

The load share mode of PRU-ICSSG is enabled for this example. Three cores—RTU-PRU, PRU, and TX-PRU—are used.

Note

Channels 6 to 8 Fast Detect is not mapped with any ICSS PWM trip zone block. This is a hardware limitation. A software-based solution can be used as described in Fast Detect trip through PRU firmware.

1. Continuous Mode Example
   
   • Continuous Normal Current sampling.
     
   • Nine channels with load share mode.
     
   • ICSS PWM trip-based Fast Detect for channels 0 to 5.
     
   • ICSS PWM trip-based Over Current detection for all nine channels.
     
     • Note: Over Current OSR should be equal to Normal Current OSR.
       
   • Each channel has an individual interrupt.
     
     • Note: Due to the unavailability of host interrupts, only the Channel 0 interrupt is configured for the TX PRU (Channels 6 to 8) in the application.
       

Important files and directory structure

Folder/Files	Description
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode	Application specific sources for ICSS SDFM for trigger based normal current sampling for three channels
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_nine_channel_with_continuous_mode	Application specific sources for ICSS SDFM for continuous normal current sampling for nine channels
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_with_continuous_mode	Application specific sources for ICSS SDFM for continuous normal current sampling for three channels
${SDK_INSTALL_PATH}/examples/current_sense	Common source for ICSS SDFM applications
${SDK_INSTALL_PATH}/source/current_sense/sdfm
firmware/	Folder containing ICSS SDFM firmware sources
driver/	ICSS SDFM driver source
include/	Folder containing ICSS SDFM structures and APIs declarations

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 freertos
ICSSG	ICSSG0
PRU	PRU0 (single channel)
	PRU0, RTU-PRU0, TXPRU0 (multi channel using three PRUs - load share mode)
Toolchain	ti-arm-clang
Board	am243x-evm, am243x-lp
Examples folder	examples/current_sense

Steps to Run the Example

Hardware Prerequisites for EVM

Other than the basic EVM setup mentioned in EVM Setup , the additional hardware listed below is required to run this demo

• TIDEP-01015 3 Axis Board
• Interface card connecting EVM and TIDEP-01015 3 Axis
• Signal generator

Note

For more design details of the TIDEP-01015 3 Axis Board, or Interface card connecting EVM and TIDEP-01015 3 Axis, please contact TI via E2E/FAE.

EVM Hardware Setup

Hardware Setup SDFM

SDFM: EVM and 3axis board setup view

Hardware Prerequisites for LP

• AMC1035EVM
• LP-AM243 Board
• Signal generator

LP Hardware Setup

LP Hardware setup

SDFM: LP setup view

Build, load and run

• When using CCS projects to build, import the CCS project and build it using the CCS project menu (see Using SDK with CCS Projects ).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

Test Case Description

Test Details	Steps	Pass/Fail Criteria
1. Normal current sample data for trigger mode	1. Run example on supported board	The drawn graph and raw data should look like the attached image
	2. Draw the graph of sdfm_ch_samples array	NC sample data
2. Normal current sample data for continuous mode	1. Run example on supported board	The drawn graph and raw data should look like the attached image
	2. Draw the graph of raw the graph of sdfm_ch_samples array	NC sample data
3. To check raw data for Single Update (64 Normal Current (NC) OSR)	1. Set NC OSR to 64	The drawn graph and raw data should look like the attached image
	2. Set single update trigger time to half of EPWM cycle time
	3. Build and run example
	4. Draw graph for Raw data	Single Update Raw data
4. To check Raw data for Double Update	1. Set NC OSR to 64	The drawn graphs and raw data should look like the attached image
	2. Enable double update
	3. Set single update trigger time to 1/4 of EPWM cycle time
	4. Set double update trigger time to 3/4 of EPWM cycle time
	5. Build and run example
	6. Draw graph for Raw data	Double Update Raw data
		The pattern of the graph should be different from the single update graph. It takes 2 samples in one EPWM cycle so the graph pattern should look more like a sine wave compared to the single update graph
5. To test SINC1/SINC2/SINC3 filter	1. Set NC OSR to 64	Raw data should have different resolution for different SINC filter
	2. Set accumulator source to SINC1/SINC2/SINC3	SINC3 raw data resolution = OSR *(SINC2 raw data resolution) = OSR*OSR*(SINC1 raw data resolution)
	3. Build and run example
6. To check Threshold comparator and Over current for continuous mode example	1. Enable Comparator filter	Trip status bit must be set for the respective pwm trip zone block and TZ_OUT pin must be high
	2. Set High Threshold to 3500 and low threshold to 2500 (low and high threshold values should be configured based on raw data resolution for 16 OSR)
	3. Set Over current and Normal current OSR to 16	High Low Threshold status bits must be constantly unset and set
	4. Probe PWMm_TZ_OUT pin
	5. Build and run example
	6. Capture signal in Logic analyzer	Trip must be triggered for the respective pwm trip zone block
7. To check NC Samples with Different NC OSR Values	1. Set NC OSR values between 8 to 256	Raw data should have different resolution for different OSR values
	2. Build and run example
	3. Observe resolution of raw data
8. To check NC samples with different sdfm clock values	1. Set NC OSR to 64	Raw data range should not exceed the OSR limits
	2. Set ecap_divider variable in sdfm_example.c file for different sd clock generation
	3. Set Sigma delta clock equal to ecap generated clock
	4. Build and run example
	5. Observe resolution of raw data
9. To check Fast detect	1. Set NC OSR to 64	Trip must be triggered for the respective pwm trip zone block
	2. Enable Fast detect and disable Comparator
	3. Set Fast Detect fields with these values { window size = 4, Zero max = 18, Zero min = 2}	Zero max/min Threshold hit bits must be constantly unset and set
	4. Build and run example	One max/min threshold hit bits must be unset
	5. 1) Observe TZ_OUT PIN. 2) Check zero/one count max & zero/one count min threshold hit bits in memory map
10.Testing with sdfm clock from EPWM	1. Make hardware setup like attached image	All test case results should match with ECAP test case results
	2. SDFM: HW set for clock from EPWM
	3. Enable "APP_EPWM1_ENABLE" macro in app_sdfm.c file
	4. Set EPWM1 output frequency to 12.5MHz or 5MHz in app_sdfm.c file
	5. Set Sigma delta clock equal to EPWM1 output frequency
	6. Build and run example
	7. Test all test cases from 1 to 5 with EPWM clock
11. To test EPWM Synchronization source	1. Set synchronization source to EPWM3	All test cases should work properly
	2. Set NC OSR to 64	The drawn graph and raw data should look like the attached image
	3. Set single update trigger time to half of EPWM cycle time
	4. Add and configure EPWM3 instance in SysConfig
	5. Build and run example
	6. Draw graph for Raw data	Single Update Raw data
12. To test SDFM clock generation from eCAP	1. Set SDCLK Generation From to eCAP
	2. SDFM Clock to 20MHz	Generated clock should come out on PRGx_ECAP0_IN_APWM_OUT signal
	3. Configure PRGx_ECAP0_IN_APWM_OUT pin inside PRU ICSSG ECAP SysConfig module
	4. Build and run example
13. To test SDFM clock generation from ICSSG PRU GPO1	1. Set SDCLK Generation From to PRU-ICSSG (PRG<k>_PRU1/0_GPI1)
	2. SDFM Clock to 20MHz	Generated clock should come out on PRG<k>_PRU1/0_GPI1 signal
	3. Build and run example
14. To test SDFM clock generation from IEP	1. Set SDCLK Generation From to IEP
	2. SDFM Clock to 20MHz	Generated clock should come out on two pins corresponding to SYNC0 and SYNC1
	3. Configure SYNC_OUT0 and SYNC_OUT0 pins inside PRU ICSSG IEP SysConfig module
	4. Build and run example

Note

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