AM243x Motor Control SDK  09.01.00
hdsl_drv.h
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1 /*
2  * Copyright (C) 2021-2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
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10  *
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12  * notice, this list of conditions and the following disclaimer in the
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18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef HDSL_DRV_H_
34 #define HDSL_DRV_H_
35 
45 /* ========================================================================== */
46 /* Include Files */
47 /* ========================================================================== */
48 
49 #include <stdio.h>
50 #include <stdlib.h>
51 
52 #include <kernel/dpl/DebugP.h>
53 
54 #include <drivers/pruicss.h>
55 #include <drivers/hw_include/cslr_soc.h>
56 #include <drivers/hw_include/hw_types.h>
57 
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 
62 /* ========================================================================== */
63 /* Macros & Typedefs */
64 /* ========================================================================== */
65 
66 
67 #define HDSL_MAX_CHANNELS (3U)
68 #define CHANNEL_0_ENABLED (1<<0)
69 #define CHANNEL_1_ENABLED (1<<1)
70 #define CHANNEL_2_ENABLED (1<<2)
71 
80 #define HDSL_LONG_MSG_ADDR_DIRECT (0U)
81 
82 #define HDSL_LONG_MSG_ADDR_INDIRECT (1U)
83 
93 #define HDSL_LONG_MSG_ADDR_WITHOUT_OFFSET (0U)
94 
95 #define HDSL_LONG_MSG_ADDR_WITH_OFFSET (1U)
96 
107 #define HDSL_LONG_MSG_LENGTH_0 (0U)
108 
109 #define HDSL_LONG_MSG_LENGTH_2 (1U)
110 
111 #define HDSL_LONG_MSG_LENGTH_4 (2U)
112 
113 #define HDSL_LONG_MSG_LENGTH_8 (3U)
114 
116 #define MAX_WAIT 20000
117 
118 #define HDSL_ICSSG0_INST 0U
119 #define HDSL_ICSSG1_INST 1U
120 
121 #define HWREG(x) \
122  (*((volatile uint32_t *)(x)))
123 #define HWREGB(x) \
124  (*((volatile uint8_t *)(x)))
125 #define HWREGH(x) \
126  (*((volatile uint16_t *)(x)))
127 /*TSR configuration:*/
128 
129 /*inEvent value:*/
130 /* ICSSG_0_EDC1_SYNC0 ICSSG0 IEP1 sync event 0 Pulse */
131 #define SYNCEVENT_INTRTR_IN_27 27
132 
133 /*outEvent values:*/
134 /*SYNC0_OUT Pin Selectable timesync event 24 Edge (4+(24*4)) */
135 #define SYNCEVT_RTR_SYNC28_EVT 0x64
136 /* SYNC1_OUT Pin Selectable timesync event 25 Edge (4+(25*4)) */
137 #define SYNCEVT_RTR_SYNC29_EVT 0x68
138 /* SYNC2_OUT Pin Selectable timesync event 26 Edge (4+(26*4)) */
139 #define SYNCEVT_RTR_SYNC30_EVT 0x6C
140 /* SYNC3_OUT Pin Selectable timesync event 27 Edge (4+(27*4)) */
141 #define SYNCEVT_RTR_SYNC31_EVT 0x70
142 /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */
143 #define SYNCEVT_RTR_SYNC10_EVT 0x2C
144 
145 enum {
162 };
163 
164 typedef struct HDSL_Config_s *HDSL_Handle;
165 
166 /* ========================================================================== */
167 /* Structure Declarations & Definitions */
168 /* ========================================================================== */
169 
175 typedef struct {
176  volatile uint8_t SYS_CTRL;
177  volatile uint8_t SYNC_CTRL;
178  volatile uint8_t resvd0;
179  volatile uint8_t MASTER_QM;
180  volatile uint8_t EVENT_H;
181  volatile uint8_t EVENT_L;
182  volatile uint8_t MASK_H;
183  volatile uint8_t MASK_L;
184  volatile uint8_t MASK_SUM;
185  volatile uint8_t EDGES;
186  volatile uint8_t DELAY;
187  volatile uint8_t VERSION;
188  volatile uint8_t resvd1;
189  volatile uint8_t ENC_ID2;
190  volatile uint8_t ENC_ID1;
191  volatile uint8_t ENC_ID0;
192  volatile uint8_t POS4;
193  volatile uint8_t POS3;
194  volatile uint8_t POS2;
195  volatile uint8_t POS1;
196  volatile uint8_t POS0;
197  volatile uint8_t VEL2;
198  volatile uint8_t VEL1;
199  volatile uint8_t VEL0;
200  volatile uint8_t resvd2;
201  volatile uint8_t VPOS4;
202  volatile uint8_t VPOS3;
203  volatile uint8_t VPOS2;
204  volatile uint8_t VPOS1;
205  volatile uint8_t VPOS0;
206  volatile uint8_t VPOSCRC_H;
207  volatile uint8_t VPOSCRC_L;
208  volatile uint8_t PC_BUFFER0;
209  volatile uint8_t PC_BUFFER1;
210  volatile uint8_t PC_BUFFER2;
211  volatile uint8_t PC_BUFFER3;
212  volatile uint8_t PC_BUFFER4;
213  volatile uint8_t PC_BUFFER5;
214  volatile uint8_t PC_BUFFER6;
215  volatile uint8_t PC_BUFFER7;
216  volatile uint8_t PC_ADD_H;
217  volatile uint8_t PC_ADD_L;
218  volatile uint8_t PC_OFF_H;
219  volatile uint8_t PC_OFF_L;
220  volatile uint8_t PC_CTRL;
221  volatile uint8_t PIPE_S;
222  volatile uint8_t PIPE_D;
223  volatile uint8_t PC_DATA;
224  volatile uint8_t resvd3;
225  volatile uint8_t resvd4;
226  volatile uint8_t resvd5;
227  volatile uint8_t resvd6;
228  volatile uint8_t resvd7;
229  volatile uint8_t SAFE_CTRL;
230  volatile uint8_t SAFE_SUM;
231  volatile uint8_t S_PC_DATA;
232  volatile uint8_t ACC_ERR_CNT;
233  volatile uint8_t resvd8;
234  volatile uint8_t resvd9;
235  volatile uint8_t resvd10;
236  volatile uint8_t resvd11;
237  volatile uint8_t EVENT_S;
238  volatile uint8_t MASK_S;
239  volatile uint8_t DUMMY;
240  volatile uint8_t SLAVE_REG_CTRL;
241  volatile uint8_t ACC_ERR_CNT_THRESH;
242  volatile uint8_t resvd12;
243  volatile uint8_t resvd13;
244  /*Safe 2 Interface */
245  volatile uint8_t VERSION2;
246  volatile uint8_t ENC2_ID;
247  volatile uint8_t STATUS2;
248  volatile uint8_t VPOS24;
249  volatile uint8_t VPOS23;
250  volatile uint8_t VPOS22;
251  volatile uint8_t VPOS21;
252  volatile uint8_t VPOS20;
253  volatile uint8_t VPOSCRC2_H;
254  volatile uint8_t VPOSCRC2_L;
255  volatile uint8_t POSTX;
256  volatile uint8_t resvd14;
257  /* Online Status*/
258  volatile uint8_t ONLINE_STATUS_D_H;
259  volatile uint8_t ONLINE_STATUS_D_L;
260  volatile uint8_t ONLINE_STATUS_1_H;
261  volatile uint8_t ONLINE_STATUS_1_L;
262  volatile uint8_t ONLINE_STATUS_2_H;
263  volatile uint8_t ONLINE_STATUS_2_L;
272 typedef struct HDSL_Config_s {
273  PRUICSS_Handle icssgHandle;
275  uint32_t icssCore;
279  uint32_t *baseMemAddr; // icssgHandle->hwAttrs->baseAddr + PRUICSS_DATARAM(PRUICSS_PRUx)
283  uint32_t multi_turn;
285  uint32_t res;
287  uint64_t mask;
290  // intc_initdata // ** - needs to be common for all channels and fixed (configure for all 3 channels in starting)
291 
292 } HDSL_Config;
301 typedef struct HDSL_CopyTable_s {
302  uint32_t reserved1;
303  uint32_t loadAddr1;
304  uint32_t runAddr1;
305  uint32_t size1;
306  uint32_t reserved2;
307  uint32_t loadAddr2;
308  uint32_t runAddr2;
309  uint32_t size2;
313 /* ========================================================================== */
314 /* Function Declarations */
315 /* ========================================================================== */
323 void hdsl_enable_load_share_mode(void *pruCfg ,uint32_t pruSlice);
324 
335 HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore, uint8_t pruMode);
336 
343 void HDSL_iep_init(HDSL_Handle hdslHandle);
344 
357 int HDSL_enable_sync_signal(uint8_t ES, uint32_t period);
358 
367 uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id);
368 
375 uint8_t HDSL_get_qm(HDSL_Handle hdslHandle);
376 
384 uint16_t HDSL_get_events(HDSL_Handle hdslHandle);
385 
394 uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle);
395 
396 
406 
416 
426 
434 uint8_t HDSL_get_sum(HDSL_Handle hdslHandle);
435 
443 uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle);
444 
452 uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle);
453 
465 int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t data, uint64_t timeout);
466 
478 int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t *data, uint64_t timeout);
479 
495 int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout);
496 
511 int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout);
512 
521 void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data);
522 
531 uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off);
532 
541 uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle);
542 
550 void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val);
551 
559 uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle);
560 
568 uint8_t HDSL_get_edges(HDSL_Handle hdslHandle);
569 
577 uint8_t HDSL_get_delay(HDSL_Handle hdslHandle);
578 
587 uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte);
588 
596 
604 void* HDSL_get_src_loc(HDSL_Handle hdslHandle);
605 
613 uint32_t HDSL_get_length(HDSL_Handle hdslHandle);
614 
624 int32_t HDSL_config_copy_table(HDSL_Handle hdslHandle, HDSL_CopyTable *copyTable);
625 
626 
636 int32_t HDSL_config_channel_mask(HDSL_Handle hdslHandle, uint8_t channelMask);
637 
638 #ifdef __cplusplus
639 }
640 #endif
641 
643 #endif
HDSL_Config
Definition: hdsl_drv.h:272
HDSL_Interface::POSTX
volatile uint8_t POSTX
Definition: hdsl_drv.h:255
HDSL_Interface::resvd3
volatile uint8_t resvd3
Definition: hdsl_drv.h:224
MENU_SAFE_POSITION
@ MENU_SAFE_POSITION
Definition: hdsl_drv.h:146
HDSL_iep_init
void HDSL_iep_init(HDSL_Handle hdslHandle)
Initialize IEP and Use OCP as IEP CLK src.
HDSL_Interface::VPOSCRC2_L
volatile uint8_t VPOSCRC2_L
Definition: hdsl_drv.h:254
HDSL_Interface::PC_OFF_H
volatile uint8_t PC_OFF_H
Definition: hdsl_drv.h:218
HDSL_Interface::VERSION
volatile uint8_t VERSION
Definition: hdsl_drv.h:187
HDSL_read_pc_long_msg
int32_t HDSL_read_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout)
Trigger a long message read operation using parameters channel If this API returns SystemP_SUCCESS,...
HDSL_Interface::resvd2
volatile uint8_t resvd2
Definition: hdsl_drv.h:200
HDSL_Interface::ONLINE_STATUS_D_H
volatile uint8_t ONLINE_STATUS_D_H
Definition: hdsl_drv.h:258
HDSL_Interface::VPOS20
volatile uint8_t VPOS20
Definition: hdsl_drv.h:252
HDSL_CopyTable::reserved2
uint32_t reserved2
Definition: hdsl_drv.h:306
HDSL_open
HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore, uint8_t pruMode)
Open HDSL handle for the specified core (interrupt mapping should already be completed)
HDSL_Interface::VPOS23
volatile uint8_t VPOS23
Definition: hdsl_drv.h:249
HDSL_Config::baseMemAddr
uint32_t * baseMemAddr
Definition: hdsl_drv.h:279
MENU_DIRECT_READ_RID81_LENGTH8
@ MENU_DIRECT_READ_RID81_LENGTH8
Definition: hdsl_drv.h:155
HDSL_Interface::SAFE_CTRL
volatile uint8_t SAFE_CTRL
Definition: hdsl_drv.h:229
HDSL_enable_sync_signal
int HDSL_enable_sync_signal(uint8_t ES, uint32_t period)
Enable IEP *Enable SYNC0 and program pulse width Enable cyclic mod Program CMP1 TSR configura...
HDSL_Interface::EVENT_L
volatile uint8_t EVENT_L
Definition: hdsl_drv.h:181
HDSL_Interface::resvd14
volatile uint8_t resvd14
Definition: hdsl_drv.h:256
HDSL_Interface::resvd11
volatile uint8_t resvd11
Definition: hdsl_drv.h:236
HDSL_Config::icssCore
uint32_t icssCore
Definition: hdsl_drv.h:275
HDSL_Interface::resvd1
volatile uint8_t resvd1
Definition: hdsl_drv.h:188
HDSL_Interface::EDGES
volatile uint8_t EDGES
Definition: hdsl_drv.h:185
HDSL_write_pc_buffer
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off, uint8_t data)
Write Parameters channel buffer for different bytes(bytes 0-7)
HDSL_Interface::PC_BUFFER5
volatile uint8_t PC_BUFFER5
Definition: hdsl_drv.h:213
HDSL_get_sync_ctrl
uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle)
Returns Synchronization control value.
HDSL_Config::mask
uint64_t mask
Definition: hdsl_drv.h:287
HDSL_Interface::PC_ADD_H
volatile uint8_t PC_ADD_H
Definition: hdsl_drv.h:216
MENU_PC_SHORT_MSG_WRITE
@ MENU_PC_SHORT_MSG_WRITE
Definition: hdsl_drv.h:152
HDSL_Interface::ONLINE_STATUS_1_H
volatile uint8_t ONLINE_STATUS_1_H
Definition: hdsl_drv.h:260
HDSL_Interface::VPOS0
volatile uint8_t VPOS0
Definition: hdsl_drv.h:205
HDSL_Interface::resvd10
volatile uint8_t resvd10
Definition: hdsl_drv.h:235
HDSL_Interface
Definition: hdsl_drv.h:175
HDSL_Interface::VPOSCRC_H
volatile uint8_t VPOSCRC_H
Definition: hdsl_drv.h:206
HDSL_Interface::VPOS3
volatile uint8_t VPOS3
Definition: hdsl_drv.h:202
HDSL_Interface::resvd0
volatile uint8_t resvd0
Definition: hdsl_drv.h:178
MENU_DIRECT_READ_RID0_LENGTH4
@ MENU_DIRECT_READ_RID0_LENGTH4
Definition: hdsl_drv.h:154
HDSL_config_channel_mask
int32_t HDSL_config_channel_mask(HDSL_Handle hdslHandle, uint8_t channelMask)
Configure the channel mask.
HDSL_Config::res
uint32_t res
Definition: hdsl_drv.h:285
HDSL_CopyTable::loadAddr2
uint32_t loadAddr2
Definition: hdsl_drv.h:307
HDSL_get_acc_err_cnt
uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle)
Acceleration error counter.
HDSL_Interface::resvd6
volatile uint8_t resvd6
Definition: hdsl_drv.h:227
HDSL_set_sync_ctrl
void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val)
Writes Synchronization control value.
HDSL_Interface::ENC_ID2
volatile uint8_t ENC_ID2
Definition: hdsl_drv.h:189
HDSL_get_sum
uint8_t HDSL_get_sum(HDSL_Handle hdslHandle)
Getting Summarized slave status.
HDSL_Interface::ONLINE_STATUS_2_H
volatile uint8_t ONLINE_STATUS_2_H
Definition: hdsl_drv.h:262
HDSL_Interface::POS0
volatile uint8_t POS0
Definition: hdsl_drv.h:196
HDSL_Interface::PC_DATA
volatile uint8_t PC_DATA
Definition: hdsl_drv.h:223
HDSL_Interface::S_PC_DATA
volatile uint8_t S_PC_DATA
Definition: hdsl_drv.h:231
HDSL_Interface::MASTER_QM
volatile uint8_t MASTER_QM
Definition: hdsl_drv.h:179
HDSL_Interface::SAFE_SUM
volatile uint8_t SAFE_SUM
Definition: hdsl_drv.h:230
HDSL_Interface::EVENT_H
volatile uint8_t EVENT_H
Definition: hdsl_drv.h:180
HDSL_get_src_loc
void * HDSL_get_src_loc(HDSL_Handle hdslHandle)
Get memory location for HDSL interface struct.
HDSL_Interface::ONLINE_STATUS_1_L
volatile uint8_t ONLINE_STATUS_1_L
Definition: hdsl_drv.h:261
MENU_HDSL_REG_INTO_MEMORY
@ MENU_HDSL_REG_INTO_MEMORY
Definition: hdsl_drv.h:159
HDSL_Interface::resvd5
volatile uint8_t resvd5
Definition: hdsl_drv.h:226
HDSL_Interface::PIPE_S
volatile uint8_t PIPE_S
Definition: hdsl_drv.h:221
MENU_EVENTS
@ MENU_EVENTS
Definition: hdsl_drv.h:148
HDSL_Interface::resvd4
volatile uint8_t resvd4
Definition: hdsl_drv.h:225
HDSL_Interface::ACC_ERR_CNT
volatile uint8_t ACC_ERR_CNT
Definition: hdsl_drv.h:232
HDSL_get_edges
uint8_t HDSL_get_edges(HDSL_Handle hdslHandle)
Returns Cable bit sampling time control.
HDSL_Interface::PC_OFF_L
volatile uint8_t PC_OFF_L
Definition: hdsl_drv.h:219
HDSL_Config::multi_turn
uint32_t multi_turn
Definition: hdsl_drv.h:283
HDSL_Interface::VPOS1
volatile uint8_t VPOS1
Definition: hdsl_drv.h:204
HDSL_Interface::SLAVE_REG_CTRL
volatile uint8_t SLAVE_REG_CTRL
Definition: hdsl_drv.h:240
MENU_INVALID
@ MENU_INVALID
Definition: hdsl_drv.h:161
HDSL_get_pos
uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id)
Calculate fast position,safe position1,safe position2.
HDSL_Interface::PC_BUFFER2
volatile uint8_t PC_BUFFER2
Definition: hdsl_drv.h:210
HDSL_Interface::VPOS24
volatile uint8_t VPOS24
Definition: hdsl_drv.h:248
HDSL_Interface::VPOSCRC_L
volatile uint8_t VPOSCRC_L
Definition: hdsl_drv.h:207
HDSL_Interface::MASK_H
volatile uint8_t MASK_H
Definition: hdsl_drv.h:182
HDSL_Interface::MASK_S
volatile uint8_t MASK_S
Definition: hdsl_drv.h:238
HDSL_Interface::resvd7
volatile uint8_t resvd7
Definition: hdsl_drv.h:228
HDSL_get_enc_id
uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte)
Read encoder id bytes(byte no. 0-2)
HDSL_Interface::PC_BUFFER1
volatile uint8_t PC_BUFFER1
Definition: hdsl_drv.h:209
MENU_INDIRECT_WRITE_RID0_LENGTH8
@ MENU_INDIRECT_WRITE_RID0_LENGTH8
Definition: hdsl_drv.h:158
HDSL_Interface::PC_BUFFER6
volatile uint8_t PC_BUFFER6
Definition: hdsl_drv.h:214
HDSL_Interface::PC_BUFFER0
volatile uint8_t PC_BUFFER0
Definition: hdsl_drv.h:208
HDSL_get_rssi
uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle)
Read RSSI value.
HDSL_Interface::resvd13
volatile uint8_t resvd13
Definition: hdsl_drv.h:243
HDSL_Interface::ENC_ID0
volatile uint8_t ENC_ID0
Definition: hdsl_drv.h:191
HDSL_Interface::PIPE_D
volatile uint8_t PIPE_D
Definition: hdsl_drv.h:222
HDSL_Interface::ONLINE_STATUS_D_L
volatile uint8_t ONLINE_STATUS_D_L
Definition: hdsl_drv.h:259
HDSL_config_copy_table
int32_t HDSL_config_copy_table(HDSL_Handle hdslHandle, HDSL_CopyTable *copyTable)
Configure the copy table entries for two overlayed firmware parts for channel 2.
HDSL_Handle
struct HDSL_Config_s * HDSL_Handle
Definition: hdsl_drv.h:164
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
@ MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
Definition: hdsl_drv.h:157
HDSL_Interface::resvd9
volatile uint8_t resvd9
Definition: hdsl_drv.h:234
HDSL_get_qm
uint8_t HDSL_get_qm(HDSL_Handle hdslHandle)
Getting quality monitoring value.
HDSL_Interface::VERSION2
volatile uint8_t VERSION2
Definition: hdsl_drv.h:245
HDSL_get_length
uint32_t HDSL_get_length(HDSL_Handle hdslHandle)
Get size of memory used by HDSL interface struct.
HDSL_CopyTable::size1
uint32_t size1
Definition: hdsl_drv.h:305
HDSL_write_pc_long_msg
int32_t HDSL_write_pc_long_msg(HDSL_Handle hdslHandle, uint16_t addr, uint8_t offsetEnable, uint8_t addrType, uint8_t length, uint16_t offset, uint64_t timeout)
Trigger a long message write operation using parameters channel. Call HDSL_write_pc_buffer before thi...
HDSL_Interface::MASK_SUM
volatile uint8_t MASK_SUM
Definition: hdsl_drv.h:184
HDSL_Config::icssgHandle
PRUICSS_Handle icssgHandle
Definition: hdsl_drv.h:273
HDSL_get_online_status_d
uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::EVENT_S
volatile uint8_t EVENT_S
Definition: hdsl_drv.h:237
HDSL_Interface::DELAY
volatile uint8_t DELAY
Definition: hdsl_drv.h:186
HDSL_Interface::ENC_ID1
volatile uint8_t ENC_ID1
Definition: hdsl_drv.h:190
HDSL_Interface::VPOS2
volatile uint8_t VPOS2
Definition: hdsl_drv.h:203
HDSL_Interface::PC_ADD_L
volatile uint8_t PC_ADD_L
Definition: hdsl_drv.h:217
HDSL_Interface::ACC_ERR_CNT_THRESH
volatile uint8_t ACC_ERR_CNT_THRESH
Definition: hdsl_drv.h:241
HDSL_CopyTable::loadAddr1
uint32_t loadAddr1
Definition: hdsl_drv.h:303
HDSL_get_online_status_1
uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::POS3
volatile uint8_t POS3
Definition: hdsl_drv.h:193
HDSL_Interface::PC_BUFFER4
volatile uint8_t PC_BUFFER4
Definition: hdsl_drv.h:212
HDSL_Interface::resvd8
volatile uint8_t resvd8
Definition: hdsl_drv.h:233
HDSL_read_pc_buffer
uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off)
Returns Parameters channel buffer for different bytes(bytes 0-7)
HDSL_get_safe_events
uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle)
Taking values of Safe Event (EVENT_S) register.
HDSL_CopyTable::runAddr1
uint32_t runAddr1
Definition: hdsl_drv.h:304
HDSL_get_online_status_2
uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::VPOS4
volatile uint8_t VPOS4
Definition: hdsl_drv.h:201
HDSL_Interface::VEL1
volatile uint8_t VEL1
Definition: hdsl_drv.h:198
HDSL_Interface::resvd12
volatile uint8_t resvd12
Definition: hdsl_drv.h:242
HDSL_Interface::ONLINE_STATUS_2_L
volatile uint8_t ONLINE_STATUS_2_L
Definition: hdsl_drv.h:263
HDSL_read_pc_short_msg
int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t *data, uint64_t timeout)
Trigger a short message read operation using parameters channel.
HDSL_CopyTable::runAddr2
uint32_t runAddr2
Definition: hdsl_drv.h:308
MENU_SUMMARY
@ MENU_SUMMARY
Definition: hdsl_drv.h:149
HDSL_CopyTable
Definition: hdsl_drv.h:301
hdsl_enable_load_share_mode
void hdsl_enable_load_share_mode(void *pruCfg, uint32_t pruSlice)
enable load share mode for multi-channel HDSL
HDSL_get_delay
uint8_t HDSL_get_delay(HDSL_Handle hdslHandle)
Returns Run time delay of system cable and signal strength.
HDSL_Config::hdslInterface
HDSL_Interface * hdslInterface
Definition: hdsl_drv.h:281
MENU_LIMIT
@ MENU_LIMIT
Definition: hdsl_drv.h:160
MENU_DIRECT_READ_RID81_LENGTH2
@ MENU_DIRECT_READ_RID81_LENGTH2
Definition: hdsl_drv.h:156
HDSL_Interface::SYS_CTRL
volatile uint8_t SYS_CTRL
Definition: hdsl_drv.h:176
HDSL_Interface::POS2
volatile uint8_t POS2
Definition: hdsl_drv.h:194
MENU_RSSI
@ MENU_RSSI
Definition: hdsl_drv.h:151
HDSL_Interface::PC_CTRL
volatile uint8_t PC_CTRL
Definition: hdsl_drv.h:220
HDSL_Interface::POS4
volatile uint8_t POS4
Definition: hdsl_drv.h:192
HDSL_Interface::PC_BUFFER7
volatile uint8_t PC_BUFFER7
Definition: hdsl_drv.h:215
HDSL_Interface::POS1
volatile uint8_t POS1
Definition: hdsl_drv.h:195
HDSL_Interface::VPOS21
volatile uint8_t VPOS21
Definition: hdsl_drv.h:251
HDSL_generate_memory_image
void HDSL_generate_memory_image(HDSL_Handle hdslHandle)
Generates memory image.
HDSL_Interface::SYNC_CTRL
volatile uint8_t SYNC_CTRL
Definition: hdsl_drv.h:177
HDSL_Interface::ENC2_ID
volatile uint8_t ENC2_ID
Definition: hdsl_drv.h:246
HDSL_get_events
uint16_t HDSL_get_events(HDSL_Handle hdslHandle)
Taking values of High bytes event (EVENT_H) and Low bytes event(EVENT_L)
MENU_QUALITY_MONITORING
@ MENU_QUALITY_MONITORING
Definition: hdsl_drv.h:147
HDSL_Interface::PC_BUFFER3
volatile uint8_t PC_BUFFER3
Definition: hdsl_drv.h:211
MENU_ACC_ERR_CNT
@ MENU_ACC_ERR_CNT
Definition: hdsl_drv.h:150
HDSL_Interface::VEL0
volatile uint8_t VEL0
Definition: hdsl_drv.h:199
HDSL_CopyTable::reserved1
uint32_t reserved1
Definition: hdsl_drv.h:302
HDSL_Interface::MASK_L
volatile uint8_t MASK_L
Definition: hdsl_drv.h:183
MENU_PC_SHORT_MSG_READ
@ MENU_PC_SHORT_MSG_READ
Definition: hdsl_drv.h:153
HDSL_Interface::DUMMY
volatile uint8_t DUMMY
Definition: hdsl_drv.h:239
HDSL_CopyTable::size2
uint32_t size2
Definition: hdsl_drv.h:309
HDSL_Interface::VPOSCRC2_H
volatile uint8_t VPOSCRC2_H
Definition: hdsl_drv.h:253
HDSL_write_pc_short_msg
int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t data, uint64_t timeout)
Trigger a short message write operation using parameters channel.
HDSL_Interface::STATUS2
volatile uint8_t STATUS2
Definition: hdsl_drv.h:247
HDSL_Interface::VPOS22
volatile uint8_t VPOS22
Definition: hdsl_drv.h:250
HDSL_get_master_qm
uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle)
Returns Quality monitoring value.
HDSL_Interface::VEL2
volatile uint8_t VEL2
Definition: hdsl_drv.h:197