SDFM Interface Design

Table of Contents

• Introduction
• System Overview
• Implementation
  • Specifications
  • ICSS SDFM PRU hardware
  • ICSS SDFM Firmware Implementation
    • Firmware Architecture
      • Normal Curent (NC)
      • Over Current (OC)/Threshold Comparator
    • Sync with EPWM and trigger timing
    • Fast Detect and Trip generation
    • Data/Clock Phase Compensation
    • AM64x/AM243x EVM Pin-Multiplexing
    • AM243x LP Pin-Multiplexing

Introduction

This design implements Sigma delta interface on TI Sitara™ AM64x/AM243x. ICSS SDFM is a Sigma delta filter for phase current measurement. Only two lines are required for each channel, differential pair each for SDFM clock & SDFM data. Clock is provided by external device or internal device and data comes from sigma delta modulator in form of digital bit stream.

System Overview

Implementation

The Sigma delta filter is implemented on TI Sitara™ Devices. Design is split into three parts – Sigma delta hardware support in PRU, firmware running in PRU and driver running in ARM. Application is supposed to use the ICSS SDFM driver APIs to leverage SDFM functionality. SDK example uses the SDFM hardware capability in Slice 1 of PRU-ICSSG0.

Specifications

Parameter	Default Value	Details
Normal Current Over-samping Ratio (OSR)	64	Tested with 16, 32, 64, 128 and 256
Over Current OSR	16	Tested with 16, 32, 64, 128 and 256
Sigma Delta Modulator Clock	20 MHz	Tested with 5MHz, 10MHz and 20MHz from clock from PRU-ICSSG ECAP and 5MHz clock from SoC EPWM1
Simulated EPWM frequency	8 KHz	Tested up to 20KHz
IEP frequency	300 MHz	Tested with 200MHz, 225MHz and 300MHz

ICSS SDFM PRU hardware

Refer section 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering in Technical Reference Manual(TRM) of AM243x for details.

ICSS SDFM Firmware Implementation

Following section describes the firmware implementation of Sigma Delta Decimation Filter on PRU-ICSS.

Firmware Architecture

Overall Block Diagram

• Firmware first clears the PRU registers and task manager.
• Next if phase compensation is enabled, it measures phase delay
• Then it waits for the ARM core to set SDFM enable bit. After the enable bit is set, it sends an acknowledgement to ARM core.
• After this, the firmware does initialization of PRU-ICSSG's SDFM hardware interface, task manager and IEP0.
• If threshold comparator is enabled, then a free run over current loop is setup, else it sets up an infinite waiting loop. In over current loop, the firmware reads sample data from the shadow copy register and does low and high theshold compersion with sample data, and depending on the configuration it generates over current trip in PWM trip zone block. Also if zero cross detection is enabled, it detects zero cross.
• Time triggered normal current task is configured to be triggered based on IEP CMP event. When the CMP event hits, the task manager sets the program counter to normal current task. In normal current task, firmware reads sample data from accumulator and it checks for fourth normal current sample (for SINC3 filtering). If the current normal current sample belongs to fourth normal current sample, then it stores the same in data memory DMEM as normal current row data and trigger interrupt.
• At the end of normal current firmware task, execution flow comes into infinite waiting loop or over current loop.

Normal Curent (NC)

This section describes normal current implementation.

There are two different variations of normal current.

• Trigger based: It starts execution when the trigger point is acquired (first time CMP event hits) and performs four continuous samplings to bring the accumulator and differntiator registers to stable state for the configured normal current OSR. Initially the CMP register is configured with the first sample trigger start time and then until the next third continuous normal current sample it is updated with the normal current OSR sampling time. At the end of the fourth normal current sample again, it is updated with the second sample start time if double update is enabled otherwise with the first sample trigger start time.
• Continuous sampling: It starts execution when the first time CMP event hits. Every time it updates CMP event register with the normal current OSR sampling time for next continuous sample, store sample values in DMEM and trigger R5 interrupt.

Normal Current

Single Update

Normal current sampling is done per EPWM cycle.

Single Update

Double Update

Normal current sampling is done twice in one EPWM cycle.

Double Update

Over Current (OC)/Threshold Comparator

This section describes the over current implementation. It performs continuous sampling (free run) and when the sample value crosses the high or low threshold, the corresponding PWM trip status gets set and TZ_OUT pin goes high. It also stores high and low threshold status in DMEM for all channels, SDFM_getHighThresholdStatus API returns high threshold status for specified SDFM channel number and SDFM_getLowThresholdStatus API returns low threshold status for specified SDFM channel number.

Over current

Mapping between Over current errors and PWM TZ blocks

Zero Cross Comparator

This section describes the zero cross implementation. It compares the current sample and the previous sample values with zero cross threshold value.

There are two cases:

• Current sample value is greater than zero cross threshold value: If the latest previous sample value is less than the zc threshold value, it changes the direction of the corresponding GPIO pin from low to high otherwise keeps the GPIO in the same direction.
• Current sample value is less than zero cross threshold value: If the latest previous sample value is grather than the zc threshold value, it changes the direction of the corresponding GPIO pin from High to low otherwise keeps the GPIO in the same direction.

Zero cross

Zero cross GPIO behaviour

Sync with EPWM and trigger timing

This section describes the EPWM to SDFM synchronization and trigger timing for each EPWM cycle. At the end of the every EPWM cycle, the EPWM generates a sync out event that resets the IEP timer. The firmware initiates normal current sampling at the sample trigger point in each EPWM cycle. It takes four consecutive samples to bring the accumulator and differentiator registers to stable state. It takes the first sample at the trigger point and the next three samples, each after ONE_SAMPLE_TIME. Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)

Sync with EPWM and trigger timing

Fast Detect and Trip generation

The Fast Detect block is used for fast over current detection, it comparatively measures the number of zeros and ones presented in a programmable sliding window of 4 to 32 bits. It starts the comparison after the first 32 sample clocks. Based on the configured zero max/min count limits, it compares zero counter with these limits. If zero counter crosses limit then it sends a error signal to respective PWM Trip zone block. PWM TZ block receives this error signal and sets trip status bit to bring TZ_OUT pin output state to high.

Note: To identify the sigma delta fast detect error trip cause, SDFM_getFastDetectErrorStatus API can be used and to clear the PWM trip status, SDFM_clearPwmTripStatus API can be used.

Mapping between Fast detect errors and PWM TZ blocks

Data/Clock Phase Compensation

Following points describe the process for measurement of phase difference between clock and data

• Set PRU IO mode to GPIO mode (default) for direct capture of input data and clock pins 
• First wait for rising edge on the SD data pin, then check the nearest upcoming edge to the SD clock pin. If the nearest edge of clock pin is falling, then it measures the time between the rising edge of the data pin and the falling edge of the SD clock. Otherwise it measures time between the rising edge of both data and clock pins.
• It measures delay 8 times and repeats the measurement until the get like 8 time the same or a max variation of 1 PRU cycle.
• Based on the clock polarity, phase delay is calculated. If clock polarity and upcoming nearest edge of clock pin for rising edge of data pin are same, then final phase delay will be half SD clock duty cycle time minus calculated time. Otherwise phase delay will be SD clock one cycle period time minus calculated time
  

  Phase Compensation

AM64x/AM243x EVM Pin-Multiplexing

Pin name	Signal name	Function
GPIO_ZC_TH_CH0	MCU_SPI0_D1/B6	Ch0 High threshold output
GPIO_ZC_TH_CH1	MCU_SPI1_CS0/A7	Ch1 High threshold output
GPIO_ZC_TH_CH2	MCU_SPI1_D1/C8	Ch2 High threshold output
SD0_D	PIN_PRG0_PRU0_GPO1	Channel0 data input
SD1_D	PIN_PRG0_PRU0_GPO3	Channel1 data input
SD2_D	PIN_PRG0_PRU0_GPO5	Channel2 data input
PRG0_ECAP0_IN_APWM_OUT	PIN_PRG0_PRU1_GPO15	ECAP output frequency
GPIO_MTR_1_PWM_EN	GPMC0_AD15/Y20	Enable EPWM0 on 3-axis board
SD8_CLK	PIN_PRG0_PRU0_GPO16	Comman SDFM clock input pin

AM243x LP Pin-Multiplexing

Pin name	Signal name	Function
GPIO_ZC_TH_CH0	PRG1_PRU0_GPO18	(J7.64)Ch0 Zero cross output
GPIO_ZC_TH_CH1	PRG0_PRU1_GPO2	(J7.65)Ch1 Zero cross output
GPIO_ZC_TH_CH2	PRG0_PRU1_GPO1	(J7.67)Ch2 Zero cross output
SD0_D	PIN_PRG0_PRU0_GPO1	(J4.32)Channel0 data input
SD1_D	PIN_PRG0_PRU0_GPO3	(J2.19)Channel1 data input
SD2_D	PIN_PRG0_PRU0_GPO5	(J2.13)Channel2 data input
PRG0_ECAP0_IN_APWM_OUT	PIN_PRG0_PRU1_GPO15	(J6.59)ECAP output frequency
SD8_CLK	PIN_PRG0_PRU0_GPO16	(J1.7)Comman SDFM clock input pin
PWM0_TZ_OUT	PIN_PRG0_PRU0_GPO19	(J5.45)TZ output pin for Axis-1
PWM1_TZ_OUT	PIN_PRG0_PRU1_GPO19	(J8.76)TZ output pin for Axis-2
PWM2_TZ_OUT	PIN_PRG0_PRU1_GPO8	(J6.57)TZ output pin for Axis-3
PRG1_IEP0_EDC_SYNC_OUT0	PIN_PRG1_PRU0_GPO19	(J7.63) SYNC_OUT0
PRG1_IEP0_EDC_SYNC_OUT1	PIN_PRG1_PRU0_GPO17	(J7.65) SYNC_OUT1